Commit d641d3f4 authored by Erik Faye-Lund 's avatar Erik Faye-Lund

gallium: add PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS

This gets rid of a r600 specific hack in the state-tracker, and prepares
for other drivers to be able to use hw-atomics.

While we're at it, clean up some indentation in the various drivers.
Signed-off-by: Erik Faye-Lund 's avatarErik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh's avatarGurchetan Singh <gurchetansingh@chromium.org>
parent 84795f8c
......@@ -304,6 +304,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
return 0;
case PIPE_CAP_MAX_GS_INVOCATIONS:
......
......@@ -458,6 +458,9 @@ subpixel precision bias in bits during conservative rasterization.
TGSI_PROPERTY_GS_INVOCATIONS.
* ``PIPE_CAP_MAX_SHADER_BUFFER_SIZE``: Maximum supported size for binding
with set_shader_buffers.
* ``PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS``: Maximum total number of shader
buffers. A value of 0 means the sum of all per-shader stage maximums (see
``PIPE_SHADER_CAP_MAX_SHADER_BUFFERS``).
.. _pipe_capf:
......
......@@ -380,8 +380,12 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
/* shader buffer objects */
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
return 1 << 27;
case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
return 8;
/* Unsupported features. */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
......
......@@ -818,6 +818,7 @@ enum pipe_cap
PIPE_CAP_MAX_GS_INVOCATIONS,
PIPE_CAP_MAX_SHADER_BUFFER_SIZE,
PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE,
PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS,
};
/**
......
......@@ -470,8 +470,10 @@ void st_init_limits(struct pipe_screen *screen,
c->ShaderStorageBufferOffsetAlignment =
screen->get_param(screen, PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT);
if (c->ShaderStorageBufferOffsetAlignment) {
/* for hw atomic counters leaves these at default for now */
if (ssbo_atomic) {
c->MaxCombinedShaderStorageBlocks =
MIN2(screen->get_param(screen, PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS),
MAX_COMBINED_SHADER_STORAGE_BUFFERS);
if (!c->MaxCombinedShaderStorageBlocks) {
c->MaxCombinedShaderStorageBlocks =
c->Program[MESA_SHADER_VERTEX].MaxShaderStorageBlocks +
c->Program[MESA_SHADER_TESS_CTRL].MaxShaderStorageBlocks +
......
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