Commit ccb4ea5a authored by Neha Bhende's avatar Neha Bhende Committed by Marge Bot

svga: Add GL4.1(compatibility profile) support in svga driver

This patch is a squash commit of a very long in-house patch series.
Reviewed-by: Brian Paul's avatarBrian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee's avatarCharmaine Lee <charmainel@vmware.com>
Signed-off-by: Neha Bhende's avatarNeha Bhende <bhenden@vmware.com>
Part-of: <!5317>
parent 52ce25be
......@@ -201,7 +201,7 @@ typedef enum {
VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106,
/* GL guest */
VGPU10_OPCODE_IDIV = 107,
VGPU10_OPCODE_VMWARE = 107,
/* DX10.1 */
VGPU10_OPCODE_LOD = 108,
......
......@@ -436,8 +436,9 @@ typedef uint32 SVGA3dSurfaceFlags;
* mob-backing to store all the samples.
*/
#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38)
#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 33)
#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 42)
/*
* Surface flags types:
......@@ -464,7 +465,8 @@ typedef uint64 SVGA3dSurfaceAllFlags;
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
SVGA3D_SURFACE_VADECODE | \
SVGA3D_SURFACE_MULTISAMPLE \
SVGA3D_SURFACE_MULTISAMPLE | \
SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
)
#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
......@@ -480,7 +482,8 @@ typedef uint64 SVGA3dSurfaceAllFlags;
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
SVGA3D_SURFACE_VADECODE | \
SVGA3D_SURFACE_MULTISAMPLE \
SVGA3D_SURFACE_MULTISAMPLE | \
SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
)
#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
......@@ -508,7 +511,8 @@ typedef uint64 SVGA3dSurfaceAllFlags;
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
SVGA3D_SURFACE_VADECODE | \
SVGA3D_SURFACE_MULTISAMPLE \
SVGA3D_SURFACE_MULTISAMPLE | \
SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
)
#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
......@@ -527,7 +531,8 @@ typedef uint64 SVGA3dSurfaceAllFlags;
SVGA3D_SURFACE_VOLUME | \
SVGA3D_SURFACE_1D | \
SVGA3D_SURFACE_SCREENTARGET | \
SVGA3D_SURFACE_MOB_PITCH \
SVGA3D_SURFACE_MOB_PITCH | \
SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
)
#define SVGA3D_SURFACE_DX_ONLY_MASK \
......@@ -636,7 +641,8 @@ typedef uint64 SVGA3dSurfaceAllFlags;
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
SVGA3D_SURFACE_VADECODE | \
SVGA3D_SURFACE_MULTISAMPLE \
SVGA3D_SURFACE_MULTISAMPLE | \
SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
)
......
......@@ -36,6 +36,7 @@ files_svga = files(
'svga_pipe_flush.c',
'svga_pipe_fs.c',
'svga_pipe_gs.c',
'svga_pipe_ts.c',
'svga_pipe_misc.c',
'svga_pipe_query.c',
'svga_pipe_rasterizer.c',
......@@ -56,6 +57,7 @@ files_svga = files(
'svga_state_framebuffer.c',
'svga_state_fs.c',
'svga_state_gs.c',
'svga_state_ts.c',
'svga_state_need_swtnl.c',
'svga_state_rss.c',
'svga_state_sampler.c',
......
......@@ -697,4 +697,33 @@ SVGA3D_vgpu10_ResolveCopy(struct svga_winsys_context *swc,
struct svga_winsys_surface *src,
const SVGA3dSurfaceFormat copyFormat);
enum pipe_error
SVGA3D_sm5_DrawIndexedInstancedIndirect(struct svga_winsys_context *swc,
struct svga_winsys_surface *argBuffer,
unsigned argOffset);
enum pipe_error
SVGA3D_sm5_DrawInstancedIndirect(struct svga_winsys_context *swc,
struct svga_winsys_surface *argBuffer,
unsigned argOffset);
enum pipe_error
SVGA3D_sm5_Dispatch(struct svga_winsys_context *swc,
const uint32 threadGroupCount[3]);
enum pipe_error
SVGA3D_sm5_DispatchIndirect(struct svga_winsys_context *swc,
struct svga_winsys_surface *argBuffer,
uint32 argOffset);
enum pipe_error
SVGA3D_sm5_DefineAndBindStreamOutput(struct svga_winsys_context *swc,
SVGA3dStreamOutputId soid,
uint32 numOutputStreamEntries,
uint32 numOutputStreamStrides,
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS],
struct svga_winsys_buffer *declBuf,
uint32 rasterizedStream,
uint32 sizeInBytes);
#endif /* __SVGA3D_H__ */
......@@ -1130,7 +1130,7 @@ SVGA3D_vgpu10_DefineStreamOutput(struct svga_winsys_context *swc,
memcpy(cmd->decl, decl,
sizeof(SVGA3dStreamOutputDeclarationEntry)
* SVGA3D_MAX_STREAMOUT_DECLS);
* SVGA3D_MAX_DX10_STREAMOUT_DECLS);
cmd->rasterizedStream = 0;
swc->commit(swc);
......@@ -1432,3 +1432,159 @@ SVGA3D_vgpu10_ResolveCopy(struct svga_winsys_context *swc,
return PIPE_OK;
}
enum pipe_error
SVGA3D_sm5_DrawIndexedInstancedIndirect(struct svga_winsys_context *swc,
struct svga_winsys_surface *argBuffer,
unsigned argOffset)
{
SVGA3dCmdDXDrawIndexedInstancedIndirect *cmd =
SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT,
sizeof(SVGA3dCmdDXDrawIndexedInstancedIndirect),
1); /* one relocation */
if (!cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
swc->surface_relocation(swc, &cmd->argsBufferSid, NULL, argBuffer,
SVGA_RELOC_READ);
cmd->byteOffsetForArgs = argOffset;
swc->commit(swc);
return PIPE_OK;
}
enum pipe_error
SVGA3D_sm5_DrawInstancedIndirect(struct svga_winsys_context *swc,
struct svga_winsys_surface *argBuffer,
unsigned argOffset)
{
SVGA3dCmdDXDrawInstancedIndirect *cmd =
SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT,
sizeof(SVGA3dCmdDXDrawInstancedIndirect),
1); /* one relocation */
if (!cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
swc->surface_relocation(swc, &cmd->argsBufferSid, NULL, argBuffer,
SVGA_RELOC_READ);
cmd->byteOffsetForArgs = argOffset;
swc->commit(swc);
return PIPE_OK;
}
enum pipe_error
SVGA3D_sm5_Dispatch(struct svga_winsys_context *swc,
const uint32 threadGroupCount[3])
{
SVGA3dCmdDXDispatch *cmd;
cmd = SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_DX_DISPATCH,
sizeof(SVGA3dCmdDXDispatch),
0);
if (!cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
cmd->threadGroupCountX = threadGroupCount[0];
cmd->threadGroupCountY = threadGroupCount[1];
cmd->threadGroupCountZ = threadGroupCount[2];
swc->commit(swc);
return PIPE_OK;
}
enum pipe_error
SVGA3D_sm5_DispatchIndirect(struct svga_winsys_context *swc,
struct svga_winsys_surface *argBuffer,
uint32 argOffset)
{
SVGA3dCmdDXDispatchIndirect *cmd;
cmd = SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_DX_DISPATCH_INDIRECT,
sizeof(SVGA3dCmdDXDispatchIndirect),
1);
if (!cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
swc->surface_relocation(swc, &cmd->argsBufferSid, NULL, argBuffer,
SVGA_RELOC_READ);
cmd->byteOffsetForArgs = argOffset;
swc->commit(swc);
return PIPE_OK;
}
/**
* We don't want any flush between DefineStreamOutputWithMob and
* BindStreamOutput because it will cause partial state in command
* buffer. This function make that sure there is enough room for
* both commands before issuing them
*/
enum pipe_error
SVGA3D_sm5_DefineAndBindStreamOutput(struct svga_winsys_context *swc,
SVGA3dStreamOutputId soid,
uint32 numOutputStreamEntries,
uint32 numOutputStreamStrides,
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS],
struct svga_winsys_buffer *declBuf,
uint32 rasterizedStream,
uint32 sizeInBytes)
{
unsigned i;
SVGA3dCmdHeader *header;
SVGA3dCmdDXDefineStreamOutputWithMob *dcmd;
SVGA3dCmdDXBindStreamOutput *bcmd;
unsigned totalSize = 2 * sizeof(*header) +
sizeof(*dcmd) + sizeof(*bcmd);
/* Make sure there is room for both commands */
header = swc->reserve(swc, totalSize, 2);
if (!header)
return PIPE_ERROR_OUT_OF_MEMORY;
/* DXDefineStreamOutputWithMob command */
header->id = SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB;
header->size = sizeof(*dcmd);
dcmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)(header + 1);
dcmd->soid= soid;
dcmd->numOutputStreamEntries = numOutputStreamEntries;
dcmd->numOutputStreamStrides = numOutputStreamStrides;
dcmd->rasterizedStream = rasterizedStream;
for (i = 0; i < ARRAY_SIZE(dcmd->streamOutputStrideInBytes); i++)
dcmd->streamOutputStrideInBytes[i] = streamOutputStrideInBytes[i];
/* DXBindStreamOutput command */
header = (SVGA3dCmdHeader *)(dcmd + 1);
header->id = SVGA_3D_CMD_DX_BIND_STREAMOUTPUT;
header->size = sizeof(*bcmd);
bcmd = (SVGA3dCmdDXBindStreamOutput *)(header + 1);
bcmd->soid = soid;
bcmd->offsetInBytes = 0;
swc->mob_relocation(swc, &bcmd->mobid,
&bcmd->offsetInBytes, declBuf, 0,
SVGA_RELOC_WRITE);
bcmd->sizeInBytes = sizeInBytes;
bcmd->offsetInBytes = 0;
swc->commit(swc);
return PIPE_OK;
}
......@@ -44,6 +44,7 @@
#include "svga_debug.h"
#include "svga_state.h"
#include "svga_winsys.h"
#include "svga_streamout.h"
#define CONST0_UPLOAD_DEFAULT_SIZE 65536
......@@ -79,6 +80,9 @@ svga_destroy(struct pipe_context *pipe)
pipe->delete_blend_state(pipe, svga->noop_blend);
/* destroy stream output statistics queries */
svga_destroy_stream_output_queries(svga);
/* free query gb object */
if (svga->gb_query) {
pipe->destroy_query(pipe, NULL);
......@@ -91,6 +95,7 @@ svga_destroy(struct pipe_context *pipe)
svga_cleanup_framebuffer(svga);
svga_cleanup_tss_binding(svga);
svga_cleanup_vertex_state(svga);
svga_cleanup_tcs_state(svga);
svga_destroy_swtnl(svga);
svga_hwtnl_destroy(svga->hwtnl);
......@@ -174,12 +179,14 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
svga_init_fs_functions(svga);
svga_init_vs_functions(svga);
svga_init_gs_functions(svga);
svga_init_ts_functions(svga);
svga_init_vertex_functions(svga);
svga_init_constbuffer_functions(svga);
svga_init_query_functions(svga);
svga_init_surface_functions(svga);
svga_init_stream_output_functions(svga);
svga_init_clear_functions(svga);
svga_init_tracked_state(svga);
/* init misc state */
svga->curr.sample_mask = ~0;
......@@ -250,6 +257,7 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
memset(&svga->state.hw_clear, 0xcd, sizeof(svga->state.hw_clear));
memset(&svga->state.hw_clear.framebuffer, 0x0,
sizeof(svga->state.hw_clear.framebuffer));
memset(&svga->state.hw_clear.rtv, 0, sizeof(svga->state.hw_clear.rtv));
svga->state.hw_clear.num_rendertargets = 0;
svga->state.hw_clear.dsv = NULL;
......@@ -269,6 +277,8 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
svga->state.hw_draw.vs = NULL;
svga->state.hw_draw.gs = NULL;
svga->state.hw_draw.fs = NULL;
svga->state.hw_draw.tcs = NULL;
svga->state.hw_draw.tes = NULL;
/* Initialize the currently bound buffer resources */
memset(svga->state.hw_draw.constbuf, 0,
......@@ -303,10 +313,16 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
svga->noop_blend = svga->pipe.create_blend_state(&svga->pipe, &noop_tmpl);
}
svga->dirty = ~0;
svga->dirty = SVGA_NEW_ALL;
svga->pred.query_id = SVGA3D_INVALID_ID;
svga->disable_rasterizer = FALSE;
/**
* Create stream output statistics queries used in the workaround for auto
* draw with stream instancing.
*/
svga_create_stream_output_queries(svga);
goto done;
cleanup:
......@@ -398,6 +414,11 @@ svga_context_flush(struct svga_context *svga,
svga->rebind.flags.fs = TRUE;
svga->rebind.flags.gs = TRUE;
if (svga_have_sm5(svga)) {
svga->rebind.flags.tcs = TRUE;
svga->rebind.flags.tes = TRUE;
}
if (svga_need_to_rebind_resources(svga)) {
svga->rebind.flags.query = TRUE;
}
......@@ -447,12 +468,7 @@ svga_hwtnl_flush_retry(struct svga_context *svga)
{
enum pipe_error ret = PIPE_OK;
ret = svga_hwtnl_flush(svga->hwtnl);
if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
svga_context_flush(svga, NULL);
ret = svga_hwtnl_flush(svga->hwtnl);
}
SVGA_RETRY_OOM(svga, ret, svga_hwtnl_flush(svga->hwtnl));
assert(ret == PIPE_OK);
}
......
This diff is collapsed.
......@@ -46,6 +46,7 @@
#define DEBUG_CACHE 0x8000
#define DEBUG_STREAMOUT 0x10000
#define DEBUG_SAMPLERS 0x20000
#define DEBUG_RETRY 0x100000
#ifdef DEBUG
extern int SVGA_DEBUG;
......
This diff is collapsed.
......@@ -60,7 +60,8 @@ svga_hwtnl_vertex_buffers(struct svga_hwtnl *hwtnl,
enum pipe_error
svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
enum pipe_prim_type prim, unsigned start, unsigned count,
unsigned start_instance, unsigned instance_count);
unsigned start_instance, unsigned instance_count,
ubyte vertices_per_patch);
enum pipe_error
svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
......
......@@ -175,13 +175,14 @@ done:
static enum pipe_error
simple_draw_arrays(struct svga_hwtnl *hwtnl,
enum pipe_prim_type prim, unsigned start, unsigned count,
unsigned start_instance, unsigned instance_count)
unsigned start_instance, unsigned instance_count,
ubyte vertices_per_patch)
{
SVGA3dPrimitiveRange range;
unsigned hw_prim;
unsigned hw_count;
hw_prim = svga_translate_prim(prim, count, &hw_count);
hw_prim = svga_translate_prim(prim, count, &hw_count, vertices_per_patch);
if (hw_count == 0)
return PIPE_ERROR_BAD_INPUT;
......@@ -200,14 +201,16 @@ simple_draw_arrays(struct svga_hwtnl *hwtnl,
*/
return svga_hwtnl_prim(hwtnl, &range, count,
0, count - 1, NULL,
start_instance, instance_count);
start_instance, instance_count,
NULL, NULL);
}
enum pipe_error
svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
enum pipe_prim_type prim, unsigned start, unsigned count,
unsigned start_instance, unsigned instance_count)
unsigned start_instance, unsigned instance_count,
ubyte vertices_per_patch)
{
enum pipe_prim_type gen_prim;
unsigned gen_size, gen_nr;
......@@ -225,7 +228,7 @@ svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
}
if (svga->curr.rast->templ.flatshade &&
svga->state.hw_draw.fs->constant_color_output) {
svga_fs_variant(svga->state.hw_draw.fs)->constant_color_output) {
/* The fragment color is a constant, not per-vertex so the whole
* primitive will be the same color (except for possible blending).
* We can ignore the current provoking vertex state and use whatever
......@@ -273,7 +276,8 @@ svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
if (gen_type == U_GENERATE_LINEAR) {
ret = simple_draw_arrays(hwtnl, gen_prim, start, count,
start_instance, instance_count);
start_instance, instance_count,
vertices_per_patch);
}
else {
struct pipe_resource *gen_buf = NULL;
......@@ -299,7 +303,8 @@ svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
count - 1,
gen_prim, 0, gen_nr,
start_instance,
instance_count);
instance_count,
vertices_per_patch);
}
if (gen_buf) {
......
......@@ -186,14 +186,15 @@ svga_hwtnl_simple_draw_range_elements(struct svga_hwtnl *hwtnl,
enum pipe_prim_type prim, unsigned start,
unsigned count,
unsigned start_instance,
unsigned instance_count)
unsigned instance_count,
ubyte vertices_per_patch)
{
SVGA3dPrimitiveRange range;
unsigned hw_prim;
unsigned hw_count;
unsigned index_offset = start * index_size;
hw_prim = svga_translate_prim(prim, count, &hw_count);
hw_prim = svga_translate_prim(prim, count, &hw_count, vertices_per_patch);
if (hw_count == 0)
return PIPE_OK; /* nothing to draw */
......@@ -206,7 +207,8 @@ svga_hwtnl_simple_draw_range_elements(struct svga_hwtnl *hwtnl,
return svga_hwtnl_prim(hwtnl, &range, count,
min_index, max_index, index_buffer,
start_instance, instance_count);
start_instance, instance_count,
NULL, NULL);
}
......@@ -234,12 +236,20 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
&gen_size, &gen_nr, &gen_func);
}
else {
unsigned hw_pv;
/* There is no geometry ordering with PATCH, so no need to
* consider provoking vertex mode for the translation.
* So use the same api_pv as the hw_pv.
*/
hw_pv = info->mode == PIPE_PRIM_PATCHES ? hwtnl->api_pv :
hwtnl->hw_pv;
gen_type = u_index_translator(svga_hw_prims,
info->mode,
info->index_size,
count,
hwtnl->api_pv,
hwtnl->hw_pv,
hw_pv,
PR_DISABLE,
&gen_prim, &gen_size, &gen_nr, &gen_func);
}
......@@ -271,7 +281,8 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
info->max_index,
gen_prim, index_offset, count,
info->start_instance,
info->instance_count);
info->instance_count,
info->vertices_per_patch);
pipe_resource_reference(&index_buffer, NULL);
}
else {
......@@ -299,7 +310,8 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
gen_prim, gen_offset,
gen_nr,
info->start_instance,
info->instance_count);
info->instance_count,
info->vertices_per_patch);
}
if (gen_buf) {
......
......@@ -52,7 +52,8 @@ static const unsigned svga_hw_prims =
(1 << PIPE_PRIM_LINES_ADJACENCY) |
(1 << PIPE_PRIM_LINE_STRIP_ADJACENCY) |
(1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
(1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
(1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY) |
(1 << PIPE_PRIM_PATCHES));
/**
......@@ -64,7 +65,8 @@ static const unsigned svga_hw_prims =
* those to other types of primitives with index/translation code.
*/
static inline SVGA3dPrimitiveType
svga_translate_prim(unsigned mode, unsigned vcount, unsigned *prim_count)
svga_translate_prim(unsigned mode, unsigned vcount, unsigned *prim_count,
ubyte vertices_per_patch)
{
switch (mode) {
case PIPE_PRIM_POINTS:
......@@ -107,6 +109,13 @@ svga_translate_prim(unsigned mode, unsigned vcount, unsigned *prim_count)
*prim_count = vcount / 2 - 2 ;
return SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ;
case PIPE_PRIM_PATCHES:
*prim_count = vcount / vertices_per_patch ;
assert(vertices_per_patch >= 1);
assert(vertices_per_patch <= 32);
return (SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH - 1)
+ vertices_per_patch;
default:
assert(0);
*prim_count = 0;
......@@ -218,7 +227,9 @@ svga_hwtnl_prim(struct svga_hwtnl *hwtnl,
unsigned min_index,
unsigned max_index,
struct pipe_resource *ib,
unsigned start_instance, unsigned instance_count);
unsigned start_instance, unsigned instance_count,
const struct pipe_draw_indirect_info *indirect,
const struct pipe_stream_output_target *so_vertex_count);
enum pipe_error
svga_hwtnl_simple_draw_range_elements(struct svga_hwtnl *hwtnl,
......@@ -231,6 +242,7 @@ svga_hwtnl_simple_draw_range_elements(struct svga_hwtnl *hwtnl,
unsigned start,
unsigned count,
unsigned start_instance,
unsigned instance_count);
unsigned instance_count,
ubyte vertices_per_patch);
#endif
......@@ -71,10 +71,10 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_Z32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, SVGA3D_D32_FLOAT, 0 },
[ PIPE_FORMAT_Z24_UNORM_S8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
[ PIPE_FORMAT_Z24X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
[ PIPE_FORMAT_R32_FLOAT ] = { SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32_FLOAT ] = { SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32_FLOAT ] = { SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32_FLOAT ] = { SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32B32_FLOAT ] = { SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32B32A32_FLOAT ] = { SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32B32A32_FLOAT ] = { SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32_USCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R32G32_USCALED ] = { SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R32G32B32_USCALED ] = { SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
......@@ -176,11 +176,11 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_R16G16B16A16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
[ PIPE_FORMAT_R32_UINT ] = { SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
[ PIPE_FORMAT_R32G32_UINT ] = { SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
[ PIPE_FORMAT_R32G32B32_UINT ] = { SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_R32G32B32_UINT ] = { SVGA3D_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, 0 },
[ PIPE_FORMAT_R32G32B32A32_UINT ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
[ PIPE_FORMAT_R32_SINT ] = { SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
[ PIPE_FORMAT_R32G32_SINT ] = { SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
[ PIPE_FORMAT_R32G32B32_SINT ] = { SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_R32G32B32_SINT ] = { SVGA3D_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, 0 },
[ PIPE_FORMAT_R32G32B32A32_SINT ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
[ PIPE_FORMAT_A8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_000X },
[ PIPE_FORMAT_I8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXXX },
......@@ -2137,7 +2137,7 @@ svga_is_format_supported(struct pipe_screen *screen,
}
if (util_format_is_srgb(format) &&
(bindings & PIPE_BIND_DISPLAY_TARGET)) {
(bindings & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_RENDER_TARGET))) {
/* We only support sRGB rendering with vgpu10 */
return false;
}
......@@ -2252,6 +2252,12 @@ svga_is_dx_format_supported(struct pipe_screen *screen,
return svga_format != SVGA3D_FORMAT_INVALID;
}
if (bindings & PIPE_BIND_SAMPLER_VIEW && target == PIPE_BUFFER) {
unsigned flags;
svga_translate_texture_buffer_view_format(format, &svga_format, &flags);
return svga_format != SVGA3D_FORMAT_INVALID;
}
svga_format = svga_translate_format(ss, format, bindings);
if (svga_format == SVGA3D_FORMAT_INVALID) {
return false;
......
......@@ -87,6 +87,15 @@ svga_link_shaders(const struct tgsi_shader_info *outshader_info,
}
}
/* Find the index for position */
linkage->position_index = 0;
for (i = 0; i < outshader_info->num_outputs; i++) {
if (outshader_info->output_semantic_name[i] == TGSI_SEMANTIC_POSITION) {