Commit c0d65398 authored by Alyssa Rosenzweig's avatar Alyssa Rosenzweig Committed by Marge Bot
Browse files

panvk: Drop support for Midgard



We've discussed this at length and have agreed that Midgard + Vulkan is DOA, but
have let the code linger. Now it's getting in the way of forward progress for
PanVK... That means it's time to drop the code paths and commit t to not
supporting it.

Midgard is only *barely* Vulkan 1.0 capable, Arm's driver was mainly
experimental. Today, there are no known workloads today for hardware of that
class, given the relatively weak CPU and GPU, Linux, and arm64. Even with a
perfect Vulkan driver, FEX + DXVK on RK3399 won't be performant.

There is a risk here: in the future, 2D workloads (like desktop compositors)
might hard depend on Vulkan. It seems this is bound to happen but about a decade
out. I worry about contributing to hardware obsolescence due to missing Vulkan
drivers, however such a change would obsolete far more than Midgard v5...
There's plenty of GL2 hardware that's still alive and well, for one. It doesn't
look like Utgard will be going anywhere, even then.

For the record: I think depending on Vulkan for 2D workloads is a bad idea. It's
unfortunately on brand for some compositors.

Getting conformant Vulkan 1.0 on Midgard would be a massive amount of work on
top of conformant Bifrost/Valhall PanVK, and the performance would make it
useless for interesting 3D workloads -- especially by 2025 standards.

If there's a retrocomputing urge in the future to build a Midgard + Vulkan
driver, that could happen later. But it would be a lot more work than reverting
this commit. The compiler would need significant work to be appropriate for
anything newer than OpenGL ES 3.0, even dEQP-GLES31 tortures it pretty bad.
Support for non-32bit types is lacklustre. Piles of basic shader features in
Vulkan 1.0 are missing or broken in the Midgard compiler. Even if you got
everything working, basic extensions like subgroup ops are architecturally
impossible to implement.

On the core driver side, we would need support for indirect draws -- on Vulkan,
stalling and doing it on the CPU is a nonoption. In fact, the indirect draw code
is needed for plain indexed draws in Vulkan, meaning Zink + PanVK can be
expected to have terrible performance on anything older than Valhall. (As far as
workloads to justify building a Vulkan driver, Zink/ANGLE are the worst
examples. The existing GL driver works well and is not much work to maintain. If
it were, sticking it in Amber branch would still be less work than trying to
build a competent Vulkan driver for that hardware.)

Where does PanVK fit in? Android, for one. High end Valhall devices might run
FEX + DXVK acceptably. For whatever it's worth, Valhall is the first Mali
hardware that can support Vulkan properly, even Bifrost Vulkan is a slow mess
that you wouldn't want to use for anything if you had another option.

In theory Arm ships Vulkan drivers for this class of hardware. In practice,
Arm's drivers have long sucked on Linux, assuming you could get your hands on a
build.  It didn't take much for Panfrost to win the Linux/Mali market.

The highest end Midgard getting wide use with Panfrost is the RK3399 with the
Mali-T860, as in the Pinebook Pro. Even by today's standards, RK3399 is showing
its limits. It seems unlikely that its users in 10 years from now will also be
using Vulkan-required 2030 desktop environment eye candy. Graphically, the
nicest experience on RK3399 is sway or weston, with GLES2 renderers.
Realistically, sway won't go Vulkan-only for a long-time.

Making ourselves crazy trying to support Midgard poorly in PanVK seems like
letting perfect (Vulkan support) be the enemy of good (Vulkan support). In that
light, future developers making core 2D software Vulkan-only (forcing software
rasterization instead of using the hardware OpenGL) are doing a lot more
e-wasting than us simply not providing Midgard Vulkan drivers because we don't
have the resources to do so, and keeping the broken code in-tree will just get
in the way of forward progress for shipping PanVK at all.

There are good reasons, after all, that turnip starts with a6xx.

(If proper Vulkan support only began with Valhall, will we support Bifrost
long term? Unclear. There are some good arguments on both sides here.)

Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand's avatarJason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Boris Brezillon's avatarBoris Brezillon <boris.brezillon@collabora.com>
Part-of: <!16915>
parent 3684776f
Pipeline #607819 waiting for manual action with stages
......@@ -28,7 +28,7 @@ panvk_entrypoints = custom_target(
command : [
prog_python, '@INPUT0@', '--xml', '@INPUT1@', '--proto', '--weak',
'--out-h', '@OUTPUT0@', '--out-c', '@OUTPUT1@', '--prefix', 'panvk',
'--device-prefix', 'panvk_v5', '--device-prefix', 'panvk_v6', '--device-prefix', 'panvk_v7',
'--device-prefix', 'panvk_v6', '--device-prefix', 'panvk_v7',
],
depend_files : vk_entrypoints_gen_depend_files,
)
......@@ -55,7 +55,7 @@ panvk_deps = []
panvk_flags = []
panvk_per_arch_libs = []
foreach arch : ['5', '6', '7']
foreach arch : ['6', '7']
panvk_per_arch_libs += static_library(
'panvk_v@0@'.format(arch),
[
......
......@@ -917,7 +917,6 @@ panvk_queue_init(struct panvk_device *device,
}
switch (pdev->arch) {
case 5: queue->vk.driver_submit = panvk_v5_queue_submit; break;
case 6: queue->vk.driver_submit = panvk_v6_queue_submit; break;
case 7: queue->vk.driver_submit = panvk_v7_queue_submit; break;
default: unreachable("Invalid arch");
......@@ -971,9 +970,6 @@ panvk_CreateDevice(VkPhysicalDevice physicalDevice,
struct vk_device_dispatch_table dispatch_table;
switch (physical_device->pdev.arch) {
case 5:
dev_entrypoints = &panvk_v5_device_entrypoints;
break;
case 6:
dev_entrypoints = &panvk_v6_device_entrypoints;
break;
......
......@@ -1122,7 +1122,6 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(panvk_sampler, base, VkSampler, VK_OBJECT_TYPE_SA
#define panvk_arch_dispatch(arch, name, ...) \
do { \
switch (arch) { \
case 5: panvk_arch_name(name, v5)(__VA_ARGS__); break; \
case 6: panvk_arch_name(name, v6)(__VA_ARGS__); break; \
case 7: panvk_arch_name(name, v7)(__VA_ARGS__); break; \
default: unreachable("Invalid arch"); \
......@@ -1130,9 +1129,7 @@ do { \
} while (0)
#ifdef PAN_ARCH
#if PAN_ARCH == 5
#define panvk_per_arch(name) panvk_arch_name(name, v5)
#elif PAN_ARCH == 6
#if PAN_ARCH == 6
#define panvk_per_arch(name) panvk_arch_name(name, v6)
#elif PAN_ARCH == 7
#define panvk_per_arch(name) panvk_arch_name(name, v7)
......@@ -1142,14 +1139,6 @@ do { \
#include "panvk_vX_device.h"
#include "panvk_vX_meta.h"
#else
#define PAN_ARCH 5
#define panvk_per_arch(name) panvk_arch_name(name, v5)
#include "panvk_vX_cmd_buffer.h"
#include "panvk_vX_cs.h"
#include "panvk_vX_device.h"
#include "panvk_vX_meta.h"
#undef PAN_ARCH
#undef panvk_per_arch
#define PAN_ARCH 6
#define panvk_per_arch(name) panvk_arch_name(name, v6)
#include "panvk_vX_cmd_buffer.h"
......
......@@ -65,63 +65,6 @@ panvk_cmd_prepare_fragment_job(struct panvk_cmd_buffer *cmdbuf)
util_dynarray_append(&batch->jobs, void *, job_ptr.cpu);
}
#if PAN_ARCH == 5
void
panvk_per_arch(cmd_get_polygon_list)(struct panvk_cmd_buffer *cmdbuf,
unsigned width, unsigned height,
bool has_draws)
{
struct panfrost_device *pdev = &cmdbuf->device->physical_device->pdev;
struct panvk_batch *batch = cmdbuf->state.batch;
if (batch->tiler.ctx.midgard.polygon_list)
return;
unsigned size =
panfrost_tiler_get_polygon_list_size(pdev, width, height, has_draws);
size = util_next_power_of_two(size);
/* Create the BO as invisible if we can. In the non-hierarchical tiler case,
* we need to write the polygon list manually because there's not WRITE_VALUE
* job in the chain. */
bool init_polygon_list = !has_draws && pdev->model->quirks.no_hierarchical_tiling;
batch->tiler.ctx.midgard.polygon_list =
panfrost_bo_create(pdev, size,
panvk_debug_adjust_bo_flags(cmdbuf->device,
init_polygon_list ?
PAN_BO_INVISIBLE: 0),
"Polygon list");
if (init_polygon_list) {
assert(batch->tiler.ctx.midgard.polygon_list->ptr.cpu);
uint32_t *polygon_list_body =
batch->tiler.ctx.midgard.polygon_list->ptr.cpu +
MALI_MIDGARD_TILER_MINIMUM_HEADER_SIZE;
polygon_list_body[0] = 0xa0000000;
}
batch->tiler.ctx.midgard.disable = !has_draws;
}
#endif
#if PAN_ARCH <= 5
static void
panvk_copy_fb_desc(struct panvk_cmd_buffer *cmdbuf, void *src)
{
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
struct panvk_batch *batch = cmdbuf->state.batch;
uint32_t size = pan_size(FRAMEBUFFER);
if (fbinfo->zs.view.zs || fbinfo->zs.view.s)
size += pan_size(ZS_CRC_EXTENSION);
size += MAX2(fbinfo->rt_count, 1) * pan_size(RENDER_TARGET);
memcpy(batch->fb.desc.cpu, src, size);
}
#endif
void
panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
{
......@@ -131,11 +74,6 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
return;
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
#if PAN_ARCH <= 5
uint32_t tmp_fbd[(pan_size(FRAMEBUFFER) +
pan_size(ZS_CRC_EXTENSION) +
(MAX_RTS * pan_size(RENDER_TARGET))) / 4];
#endif
assert(batch);
......@@ -171,10 +109,8 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
struct panfrost_ptr preload_jobs[2];
unsigned num_preload_jobs =
GENX(pan_preload_fb)(&cmdbuf->desc_pool.base, &batch->scoreboard,
&cmdbuf->state.fb.info,
PAN_ARCH >= 6 ? batch->tls.gpu : batch->fb.desc.gpu,
PAN_ARCH >= 6 ? batch->tiler.descs.gpu : 0,
preload_jobs);
&cmdbuf->state.fb.info, batch->tls.gpu,
batch->tiler.descs.gpu, preload_jobs);
for (unsigned i = 0; i < num_preload_jobs; i++)
util_dynarray_append(&batch->jobs, void *, preload_jobs[i].cpu);
}
......@@ -193,42 +129,13 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
pan_pool_alloc_aligned(&cmdbuf->tls_pool.base, batch->wls_total_size, 4096).gpu;
}
if ((PAN_ARCH >= 6 || !batch->fb.desc.cpu) && batch->tls.cpu)
if (batch->tls.cpu)
GENX(pan_emit_tls)(&batch->tlsinfo, batch->tls.cpu);
if (batch->fb.desc.cpu) {
#if PAN_ARCH == 5
panvk_per_arch(cmd_get_polygon_list)(cmdbuf,
fbinfo->width,
fbinfo->height,
false);
mali_ptr polygon_list =
batch->tiler.ctx.midgard.polygon_list->ptr.gpu;
struct panfrost_ptr writeval_job =
panfrost_scoreboard_initialize_tiler(&cmdbuf->desc_pool.base,
&batch->scoreboard,
polygon_list);
if (writeval_job.cpu)
util_dynarray_append(&batch->jobs, void *, writeval_job.cpu);
#endif
#if PAN_ARCH <= 5
void *fbd = tmp_fbd;
#else
void *fbd = batch->fb.desc.cpu;
#endif
batch->fb.desc.gpu |=
GENX(pan_emit_fbd)(pdev, &cmdbuf->state.fb.info, &batch->tlsinfo,
&batch->tiler.ctx, fbd);
#if PAN_ARCH <= 5
panvk_copy_fb_desc(cmdbuf, tmp_fbd);
memcpy(batch->tiler.templ,
pan_section_ptr(fbd, FRAMEBUFFER, TILER),
pan_size(TILER_CONTEXT));
#endif
&batch->tiler.ctx, batch->fb.desc.cpu);
panvk_cmd_prepare_fragment_job(cmdbuf);
}
......@@ -286,10 +193,8 @@ panvk_per_arch(cmd_alloc_fb_desc)(struct panvk_cmd_buffer *cmdbuf)
/* Tag the pointer */
batch->fb.desc.gpu |= tags;
#if PAN_ARCH >= 6
memset(&cmdbuf->state.fb.info.bifrost.pre_post.dcds, 0,
sizeof(cmdbuf->state.fb.info.bifrost.pre_post.dcds));
#endif
}
void
......@@ -298,14 +203,7 @@ panvk_per_arch(cmd_alloc_tls_desc)(struct panvk_cmd_buffer *cmdbuf, bool gfx)
struct panvk_batch *batch = cmdbuf->state.batch;
assert(batch);
if (batch->tls.gpu)
return;
if (PAN_ARCH == 5 && gfx) {
panvk_per_arch(cmd_alloc_fb_desc)(cmdbuf);
batch->tls = batch->fb.desc;
batch->tls.gpu &= ~63ULL;
} else {
if (!batch->tls.gpu) {
batch->tls =
pan_pool_alloc_desc(&cmdbuf->desc_pool.base, LOCAL_STORAGE);
}
......@@ -413,13 +311,10 @@ panvk_cmd_prepare_textures(struct panvk_cmd_buffer *cmdbuf,
if (!num_textures || desc_state->textures)
return;
unsigned tex_entry_size = PAN_ARCH >= 6 ?
pan_size(TEXTURE) :
sizeof(mali_ptr);
struct panfrost_ptr textures =
pan_pool_alloc_aligned(&cmdbuf->desc_pool.base,
num_textures * tex_entry_size,
tex_entry_size);
num_textures * pan_size(TEXTURE),
pan_size(TEXTURE));
void *texture = textures.cpu;
......@@ -429,10 +324,10 @@ panvk_cmd_prepare_textures(struct panvk_cmd_buffer *cmdbuf,
memcpy(texture,
desc_state->sets[i]->textures,
desc_state->sets[i]->layout->num_textures *
tex_entry_size);
pan_size(TEXTURE));
texture += desc_state->sets[i]->layout->num_textures *
tex_entry_size;
pan_size(TEXTURE);
}
desc_state->textures = textures.gpu;
......@@ -458,9 +353,7 @@ panvk_cmd_prepare_samplers(struct panvk_cmd_buffer *cmdbuf,
/* Prepare the dummy sampler */
pan_pack(sampler, SAMPLER, cfg) {
#if PAN_ARCH >= 6
cfg.seamless_cube_map = false;
#endif
cfg.magnify_nearest = true;
cfg.minify_nearest = true;
cfg.normalized_coordinates = false;
......@@ -535,7 +428,6 @@ panvk_draw_prepare_fs_rsd(struct panvk_cmd_buffer *cmdbuf,
draw->fs_rsd = cmdbuf->state.fs_rsd;
}
#if PAN_ARCH >= 6
void
panvk_per_arch(cmd_get_tiler_context)(struct panvk_cmd_buffer *cmdbuf,
unsigned width, unsigned height)
......@@ -562,23 +454,15 @@ panvk_per_arch(cmd_get_tiler_context)(struct panvk_cmd_buffer *cmdbuf,
pan_size(TILER_CONTEXT) + pan_size(TILER_HEAP));
batch->tiler.ctx.bifrost = batch->tiler.descs.gpu;
}
#endif
void
panvk_per_arch(cmd_prepare_tiler_context)(struct panvk_cmd_buffer *cmdbuf)
{
const struct pan_fb_info *fbinfo = &cmdbuf->state.fb.info;
#if PAN_ARCH == 5
panvk_per_arch(cmd_get_polygon_list)(cmdbuf,
fbinfo->width,
fbinfo->height,
true);
#else
panvk_per_arch(cmd_get_tiler_context)(cmdbuf,
fbinfo->width,
fbinfo->height);
#endif
}
static void
......@@ -604,16 +488,14 @@ panvk_draw_prepare_varyings(struct panvk_cmd_buffer *cmdbuf,
unsigned buf_count = panvk_varyings_buf_count(varyings);
struct panfrost_ptr bufs =
pan_pool_alloc_desc_array(&cmdbuf->desc_pool.base,
buf_count + (PAN_ARCH >= 6 ? 1 : 0),
buf_count + 1,
ATTRIBUTE_BUFFER);
panvk_per_arch(emit_varying_bufs)(varyings, bufs.cpu);
/* We need an empty entry to stop prefetching on Bifrost */
#if PAN_ARCH >= 6
memset(bufs.cpu + (pan_size(ATTRIBUTE_BUFFER) * buf_count), 0,
pan_size(ATTRIBUTE_BUFFER));
#endif
if (BITSET_TEST(varyings->active, VARYING_SLOT_POS)) {
draw->position = varyings->buf[varyings->varying[VARYING_SLOT_POS].buf].address +
......@@ -672,7 +554,6 @@ panvk_fill_non_vs_attribs(struct panvk_cmd_buffer *cmdbuf,
pan_pack(attribs + offset, ATTRIBUTE, cfg) {
cfg.buffer_index = first_buf + (img_idx + i) * 2;
cfg.format = desc_state->sets[s]->img_fmts[i];
cfg.offset_enable = PAN_ARCH <= 5;
}
offset += pan_size(ATTRIBUTE);
}
......@@ -693,7 +574,7 @@ panvk_prepare_non_vs_attribs(struct panvk_cmd_buffer *cmdbuf,
unsigned attrib_buf_count = (pipeline->layout->num_imgs * 2);
struct panfrost_ptr bufs =
pan_pool_alloc_desc_array(&cmdbuf->desc_pool.base,
attrib_buf_count + (PAN_ARCH >= 6 ? 1 : 0),
attrib_buf_count + 1,
ATTRIBUTE_BUFFER);
struct panfrost_ptr attribs =
pan_pool_alloc_desc_array(&cmdbuf->desc_pool.base, attrib_count,
......@@ -731,7 +612,7 @@ panvk_draw_prepare_vs_attribs(struct panvk_cmd_buffer *cmdbuf,
unsigned attrib_buf_count = pipeline->attribs.buf_count * 2;
struct panfrost_ptr bufs =
pan_pool_alloc_desc_array(&cmdbuf->desc_pool.base,
attrib_buf_count + (PAN_ARCH >= 6 ? 1 : 0),
attrib_buf_count + 1,
ATTRIBUTE_BUFFER);
struct panfrost_ptr attribs =
pan_pool_alloc_desc_array(&cmdbuf->desc_pool.base, attrib_count,
......@@ -755,10 +636,8 @@ panvk_draw_prepare_vs_attribs(struct panvk_cmd_buffer *cmdbuf,
}
/* A NULL entry is needed to stop prefecting on Bifrost */
#if PAN_ARCH >= 6
memset(bufs.cpu + (pan_size(ATTRIBUTE_BUFFER) * attrib_buf_count), 0,
pan_size(ATTRIBUTE_BUFFER));
#endif
desc_state->vs_attrib_bufs = bufs.gpu;
desc_state->vs_attribs = attribs.gpu;
......@@ -1199,10 +1078,6 @@ panvk_reset_cmdbuf(struct panvk_cmd_buffer *cmdbuf)
list_for_each_entry_safe(struct panvk_batch, batch, &cmdbuf->batches, node) {
list_del(&batch->node);
util_dynarray_fini(&batch->jobs);
#if PAN_ARCH <= 5
panfrost_bo_unreference(batch->tiler.ctx.midgard.polygon_list);
#endif
util_dynarray_fini(&batch->event_ops);
vk_free(&cmdbuf->pool->vk.alloc, batch);
......@@ -1229,10 +1104,6 @@ panvk_destroy_cmdbuf(struct panvk_cmd_buffer *cmdbuf)
list_for_each_entry_safe(struct panvk_batch, batch, &cmdbuf->batches, node) {
list_del(&batch->node);
util_dynarray_fini(&batch->jobs);
#if PAN_ARCH <= 5
panfrost_bo_unreference(batch->tiler.ctx.midgard.polygon_list);
#endif
util_dynarray_fini(&batch->event_ops);
vk_free(&cmdbuf->pool->vk.alloc, batch);
......
......@@ -36,16 +36,9 @@ void
panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf);
#if PAN_ARCH <= 5
void
panvk_per_arch(cmd_get_polygon_list)(struct panvk_cmd_buffer *cmdbuf,
unsigned width, unsigned height,
bool has_draws);
#else
void
panvk_per_arch(cmd_get_tiler_context)(struct panvk_cmd_buffer *cmdbuf,
unsigned width, unsigned height);
#endif
void
panvk_per_arch(cmd_alloc_fb_desc)(struct panvk_cmd_buffer *cmdbuf);
......
......@@ -104,7 +104,6 @@ panvk_varying_hw_format(const struct panvk_device *dev,
{
const struct panfrost_device *pdev = &dev->physical_device->pdev;
gl_varying_slot loc = varyings->stage[stage].loc[idx];
bool fs = stage == MESA_SHADER_FRAGMENT;
switch (loc) {
case VARYING_SLOT_PNTC:
......@@ -116,14 +115,11 @@ panvk_varying_hw_format(const struct panvk_device *dev,
#endif
case VARYING_SLOT_POS:
#if PAN_ARCH <= 6
return ((fs ? MALI_RGBA32F : MALI_SNAP_4) << 12) |
panfrost_get_default_swizzle(4);
return (MALI_SNAP_4 << 12) | panfrost_get_default_swizzle(4);
#else
return ((fs ? MALI_RGBA32F : MALI_SNAP_4) << 12) |
MALI_RGB_COMPONENT_ORDER_RGBA;
return (MALI_SNAP_4 << 12) | MALI_RGB_COMPONENT_ORDER_RGBA;
#endif
default:
assert(!panvk_varying_is_builtin(stage, loc));
if (varyings->varying[loc].format != PIPE_FORMAT_NONE)
return pdev->formats[varyings->varying[loc].format].hw;
#if PAN_ARCH >= 7
......@@ -141,18 +137,10 @@ panvk_emit_varying(const struct panvk_device *dev,
void *attrib)
{
gl_varying_slot loc = varyings->stage[stage].loc[idx];
bool fs = stage == MESA_SHADER_FRAGMENT;
pan_pack(attrib, ATTRIBUTE, cfg) {
if (!panvk_varying_is_builtin(stage, loc)) {
cfg.buffer_index = varyings->varying[loc].buf;
cfg.offset = varyings->varying[loc].offset;
} else {
cfg.buffer_index =
panvk_varying_buf_index(varyings,
panvk_varying_buf_id(fs, loc));
}
cfg.offset_enable = PAN_ARCH == 5;
cfg.buffer_index = varyings->varying[loc].buf;
cfg.offset = varyings->varying[loc].offset;
cfg.format = panvk_varying_hw_format(dev, varyings, stage, idx);
}
}
......@@ -176,14 +164,6 @@ panvk_emit_varying_buf(const struct panvk_varyings_info *varyings,
unsigned buf_idx = panvk_varying_buf_index(varyings, id);
pan_pack(buf, ATTRIBUTE_BUFFER, cfg) {
#if PAN_ARCH == 5
enum mali_attribute_special special_id = panvk_varying_special_buf_id(id);
if (special_id) {
cfg.type = 0;
cfg.special = special_id;
continue;
}
#endif
unsigned offset = varyings->buf[buf_idx].address & 63;
cfg.stride = varyings->buf[buf_idx].stride;
......@@ -213,23 +193,6 @@ panvk_emit_attrib_buf(const struct panvk_attribs_info *info,
{
const struct panvk_attrib_buf_info *buf_info = &info->buf[idx];
#if PAN_ARCH == 5
if (buf_info->special) {
switch (buf_info->special_id) {
case PAN_VERTEX_ID:
panfrost_vertex_id(draw->padded_vertex_count, desc,
draw->instance_count > 1);
return;
case PAN_INSTANCE_ID:
panfrost_instance_id(draw->padded_vertex_count, desc,
draw->instance_count > 1);
return;
default:
unreachable("Invalid attribute ID");
}
}
#endif
assert(idx < buf_count);
const struct panvk_attrib_buf *buf = &bufs[idx];
mali_ptr addr = buf->address & ~63ULL;
......@@ -564,11 +527,7 @@ panvk_emit_tiler_dcd(const struct panvk_pipeline *pipeline,
cfg.viewport = draw->viewport;
cfg.varyings = draw->stages[MESA_SHADER_FRAGMENT].varyings;
cfg.varying_buffers = cfg.varyings ? draw->varying_bufs : 0;
#if PAN_ARCH == 5
cfg.fbd = draw->fb;
#else
cfg.thread_storage = draw->tls;
#endif
/* For all primitives but lines DRAW.flat_shading_vertex must
* be set to 0 and the provoking vertex is selected with the
......@@ -577,12 +536,7 @@ panvk_emit_tiler_dcd(const struct panvk_pipeline *pipeline,
if (pipeline->ia.topology == MALI_DRAW_MODE_LINES ||
pipeline->ia.topology == MALI_DRAW_MODE_LINE_STRIP ||
pipeline->ia.topology == MALI_DRAW_MODE_LINE_LOOP) {
/* The logic is inverted on bifrost. */
#if PAN_ARCH == 5
cfg.flat_shading_vertex = false;
#else
cfg.flat_shading_vertex = true;
#endif
}
cfg.offset_start = draw->offset_start;
......@@ -616,12 +570,10 @@ panvk_per_arch(emit_tiler_job)(const struct panvk_pipeline *pipeline,
section = pan_section_ptr(job, TILER_JOB, DRAW);
panvk_emit_tiler_dcd(pipeline, draw, section);
#if PAN_ARCH >= 6
pan_section_pack(job, TILER_JOB, TILER, cfg) {
cfg.address = draw->tiler_ctx->bifrost;
}
pan_section_pack(job, TILER_JOB, PADDING, padding);
#endif
}
void
......@@ -661,7 +613,6 @@ panvk_per_arch(emit_viewport)(const VkViewport *viewport,
}
}
#if PAN_ARCH >= 6
static enum mali_register_file_format
bifrost_blend_type_from_nir(nir_alu_type nir_type)
{
......@@ -684,7 +635,6 @@ bifrost_blend_type_from_nir(nir_alu_type nir_type)
unreachable("Unsupported blend shader type for NIR alu type");
}
}
#endif
void
panvk_per_arch(emit_blend)(const struct panvk_device *dev,
......@@ -698,9 +648,7 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
pan_pack(bd, BLEND, cfg) {
if (!blend->rt_count || !rts->equation.color_mask) {
cfg.enable = false;
#if PAN_ARCH >= 6
cfg.internal.mode = MALI_BLEND_MODE_OFF;
#endif
continue;
}
......@@ -708,14 +656,6 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
cfg.load_destination = pan_blend_reads_dest(blend->rts[rt].equation);
cfg.round_to_fb_precision = !dithered;
#if PAN_ARCH <= 5
cfg.blend_shader = false;
pan_blend_to_fixed_function_equation(blend->rts[rt].equation,
&cfg.equation);
cfg.constant =
pan_blend_get_constant(pan_blend_constant_mask(blend->rts[rt].equation),
blend->constants);
#else
const struct panfrost_device *pdev = &dev->physical_device->pdev;
const struct util_format_description *format_desc =
util_format_description(rts->format);
......@@ -754,7 +694,6 @@ panvk_per_arch(emit_blend)(const struct panvk_device *dev,
cfg.internal.fixed_function.conversion.register_format =
bifrost_blend_type_from_nir(pipeline->fs.info.bifrost.blend[rt].type);
cfg.internal.fixed_function.rt = rt;
#endif
}
}
......@@ -768,11 +707,7 @@ panvk_per_arch(emit_blend_constant)(const struct panvk_device *dev,
pan_pack(bd, BLEND, cfg) {
cfg.enable = false;
#if PAN_ARCH == 5
cfg.constant = constant;
#else
cfg.constant = constant * pipeline->blend.constant[rt].bifrost_factor;
#endif
}
}
......@@ -816,28 +751,6 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
if (pipeline->fs.required) {
pan_shader_prepare_rsd(info, pipeline->fs.address, &cfg);
#if PAN_ARCH == 5
/* If either depth or stencil is enabled, discard matters */
bool zs_enabled =
(pipeline->zs.z_test && pipeline->zs.z_compare_func != MALI_FUNC_ALWAYS) ||
pipeline->zs.s_test;
cfg.properties.work_register_count = info->work_reg_count;
cfg.properties.force_early_z =
info->fs.can_early_z && !pipeline->ms.alpha_to_coverage &&
pipeline->zs.z_compare_func == MALI_FUNC_ALWAYS;
/* Workaround a hardware errata where early-z cannot be enabled
* when discarding even when the depth buffer is read-only, by
* lying to the hardware about the discard and setting the
* reads tilebuffer? flag to compensate */
cfg.properties.shader_reads_tilebuffer =
info->fs.outputs_read ||
(!zs_enabled && info->fs.can_discard);
cfg.properties.shader_contains_discard =
zs_enabled && info->fs.can_discard;
#else
uint8_t rt_written = pipeline->fs.info.outputs_written >> FRAG_RESULT_DATA0;
uint8_t rt_mask = pipeline->fs.rt_mask;
cfg.properties.allow_forward_pixel_to_kill =
......@@ -845,19 +758,11 @@ panvk_per_arch(emit_base_fs_rsd)(const struct panvk_device *dev,
!(rt_mask & ~rt_written) &&
!pipeline->ms.alpha_to_coverage &&
!pipeline->blend.reads_dest;
#endif
} else {
cfg.properties.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION;