Commit bb45a151 authored by Marek Olšák's avatar Marek Olšák

r300g: use r300_buffer_domain everywhere

parent 19498be9
......@@ -37,11 +37,6 @@
#define VERY_VERBOSE_CS 1
#define VERY_VERBOSE_REGISTERS 1
/* XXX stolen from radeon_drm.h */
#define RADEON_GEM_DOMAIN_CPU 0x1
#define RADEON_GEM_DOMAIN_GTT 0x2
#define RADEON_GEM_DOMAIN_VRAM 0x4
/* XXX stolen from radeon_reg.h */
#define RADEON_CP_PACKET0 0x0
......
......@@ -485,11 +485,11 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
assert(tex && tex->buffer && "cbuf is marked, but NULL!");
OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_CS_TEX_RELOC(tex, surf->offset, 0, R300_DOMAIN_VRAM, 0);
OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
0, RADEON_GEM_DOMAIN_VRAM, 0);
0, R300_DOMAIN_VRAM, 0);
OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
}
......@@ -504,13 +504,13 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_CS_TEX_RELOC(tex, surf->offset, 0, R300_DOMAIN_VRAM, 0);
OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
0, RADEON_GEM_DOMAIN_VRAM, 0);
0, R300_DOMAIN_VRAM, 0);
}
OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
......@@ -570,13 +570,13 @@ static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
0, RADEON_GEM_DOMAIN_GTT, 0);
0, R300_DOMAIN_GTT, 0);
case 3:
/* pipe 2 only */
OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
0, RADEON_GEM_DOMAIN_GTT, 0);
0, R300_DOMAIN_GTT, 0);
case 2:
/* pipe 1 only */
/* As mentioned above, accomodate RV380 and older. */
......@@ -584,13 +584,13 @@ static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
1 << (caps->high_second_pipe ? 3 : 1));
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
0, RADEON_GEM_DOMAIN_GTT, 0);
0, R300_DOMAIN_GTT, 0);
case 1:
/* pipe 0 only */
OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
0, RADEON_GEM_DOMAIN_GTT, 0);
0, R300_DOMAIN_GTT, 0);
break;
default:
fprintf(stderr, "r300: Implementation error: Chipset reports %d"
......@@ -611,7 +611,7 @@ static void rv530_emit_query_end_single_z(struct r300_context *r300,
BEGIN_CS(8);
OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, R300_DOMAIN_GTT, 0);
OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
END_CS;
}
......@@ -624,10 +624,10 @@ static void rv530_emit_query_end_double_z(struct r300_context *r300,
BEGIN_CS(14);
OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, R300_DOMAIN_GTT, 0);
OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, R300_DOMAIN_GTT, 0);
OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
END_CS;
}
......@@ -808,7 +808,7 @@ void r300_emit_textures_state(struct r300_context *r300,
OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_CS_TEX_RELOC(r300_texture(allstate->sampler_views[i]->base.texture),
texstate->format.tile_config,
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
R300_DOMAIN_GTT | R300_DOMAIN_VRAM, 0, 0);
}
}
END_CS;
......@@ -858,7 +858,7 @@ void r300_emit_aos(struct r300_context* r300, unsigned offset, boolean indexed)
for (i = 0; i < aos_count; i++) {
OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
RADEON_GEM_DOMAIN_GTT, 0, 0);
R300_DOMAIN_GTT, 0, 0);
}
END_CS;
}
......@@ -883,7 +883,7 @@ void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
OUT_CS(r300->vertex_info.size |
(r300->vertex_info.size << 8));
OUT_CS(r300->vbo_offset);
OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_CS_BUF_RELOC(r300->vbo, 0, R300_DOMAIN_GTT, 0, 0);
END_CS;
}
......@@ -1070,7 +1070,7 @@ validate:
tex = r300_texture(fb->cbufs[i]->texture);
assert(tex && tex->buffer && "cbuf is marked, but NULL!");
if (!r300_add_texture(r300->rws, tex,
0, RADEON_GEM_DOMAIN_VRAM)) {
0, R300_DOMAIN_VRAM)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......@@ -1080,7 +1080,7 @@ validate:
tex = r300_texture(fb->zsbuf->texture);
assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
if (!r300_add_texture(r300->rws, tex,
0, RADEON_GEM_DOMAIN_VRAM)) {
0, R300_DOMAIN_VRAM)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......@@ -1093,7 +1093,7 @@ validate:
tex = r300_texture(texstate->sampler_views[i]->base.texture);
if (!r300_add_texture(r300->rws, tex,
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
R300_DOMAIN_GTT | R300_DOMAIN_VRAM, 0)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......@@ -1102,7 +1102,7 @@ validate:
if (r300->query_start.dirty ||
(r300->query_current && r300->query_current->begin_emitted)) {
if (!r300_add_buffer(r300->rws, r300->oqbo,
0, RADEON_GEM_DOMAIN_GTT)) {
0, R300_DOMAIN_GTT)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......@@ -1110,7 +1110,7 @@ validate:
/* ...vertex buffer for SWTCL path... */
if (r300->vbo) {
if (!r300_add_buffer(r300->rws, r300->vbo,
RADEON_GEM_DOMAIN_GTT, 0)) {
R300_DOMAIN_GTT, 0)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......@@ -1121,7 +1121,7 @@ validate:
pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
if (!r300_add_buffer(r300->rws, pbuf,
RADEON_GEM_DOMAIN_GTT, 0)) {
R300_DOMAIN_GTT, 0)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......@@ -1130,7 +1130,7 @@ validate:
/* ...and index buffer for HWTCL path. */
if (index_buffer) {
if (!r300_add_buffer(r300->rws, index_buffer,
RADEON_GEM_DOMAIN_GTT, 0)) {
R300_DOMAIN_GTT, 0)) {
r300->context.flush(&r300->context, 0, NULL);
goto validate;
}
......
......@@ -422,7 +422,7 @@ static void r300_emit_draw_elements(struct r300_context *r300,
(0 << R300_INDX_BUFFER_SKIP_SHIFT));
OUT_CS(offset_dwords << 2);
OUT_CS_BUF_RELOC(indexBuffer, count_dwords,
RADEON_GEM_DOMAIN_GTT, 0, 0);
R300_DOMAIN_GTT, 0, 0);
END_CS;
}
......
......@@ -116,7 +116,9 @@ static INLINE boolean r300_add_texture(struct r300_winsys_screen *rws,
static INLINE void r300_buffer_write_reloc(struct r300_winsys_screen *rws,
struct r300_buffer *buf,
uint32_t rd, uint32_t wd, uint32_t flags)
enum r300_buffer_domain rd,
enum r300_buffer_domain wd,
uint32_t flags)
{
if (!buf->buf)
return;
......@@ -126,7 +128,9 @@ static INLINE void r300_buffer_write_reloc(struct r300_winsys_screen *rws,
static INLINE void r300_texture_write_reloc(struct r300_winsys_screen *rws,
struct r300_texture *texture,
uint32_t rd, uint32_t wd, uint32_t flags)
enum r300_buffer_domain rd,
enum r300_buffer_domain wd,
uint32_t flags)
{
rws->write_cs_reloc(rws, texture->buffer, rd, wd, flags);
}
......
......@@ -101,8 +101,8 @@ struct r300_winsys_screen {
/* Add a pipe_resource to the list of buffer objects to validate. */
boolean (*add_buffer)(struct r300_winsys_screen *winsys,
struct r300_winsys_buffer *buf,
uint32_t rd,
uint32_t wd);
enum r300_buffer_domain rd,
enum r300_buffer_domain wd);
/* Revalidate all currently setup pipe_buffers.
......@@ -130,8 +130,8 @@ struct r300_winsys_screen {
/* Write a relocated dword to the command buffer. */
void (*write_cs_reloc)(struct r300_winsys_screen *winsys,
struct r300_winsys_buffer *buf,
uint32_t rd,
uint32_t wd,
enum r300_buffer_domain rd,
enum r300_buffer_domain wd,
uint32_t flags);
/* Finish a command emit. */
......
......@@ -64,11 +64,13 @@ struct pb_manager *
radeon_drm_bufmgr_create(struct radeon_libdrm_winsys *rws);
boolean radeon_drm_bufmgr_add_buffer(struct pb_buffer *_buf,
uint32_t rd, uint32_t wd);
enum r300_buffer_domain rd,
enum r300_buffer_domain wd);
void radeon_drm_bufmgr_write_reloc(struct pb_buffer *_buf,
uint32_t rd, uint32_t wd,
enum r300_buffer_domain rd,
enum r300_buffer_domain wd,
uint32_t flags);
struct pb_buffer *radeon_drm_bufmgr_create_buffer_from_handle(struct pb_manager *_mgr,
......
......@@ -339,27 +339,45 @@ void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf,
}
}
static uint32_t gem_domain(enum r300_buffer_domain dom)
{
uint32_t res = 0;
if (dom & R300_DOMAIN_GTT)
res |= RADEON_GEM_DOMAIN_GTT;
if (dom & R300_DOMAIN_VRAM)
res |= RADEON_GEM_DOMAIN_VRAM;
return res;
}
boolean radeon_drm_bufmgr_add_buffer(struct pb_buffer *_buf,
uint32_t rd, uint32_t wd)
enum r300_buffer_domain rd,
enum r300_buffer_domain wd)
{
struct radeon_drm_buffer *buf = get_drm_buffer(_buf);
uint32_t gem_rd = gem_domain(rd);
uint32_t gem_wd = gem_domain(wd);
radeon_cs_space_add_persistent_bo(buf->mgr->rws->cs, buf->bo,
rd, wd);
gem_rd, gem_wd);
return TRUE;
}
void radeon_drm_bufmgr_write_reloc(struct pb_buffer *_buf,
uint32_t rd, uint32_t wd,
enum r300_buffer_domain rd,
enum r300_buffer_domain wd,
uint32_t flags)
{
struct radeon_drm_buffer *buf = get_drm_buffer(_buf);
int retval;
uint32_t gem_rd = gem_domain(rd);
uint32_t gem_wd = gem_domain(wd);
retval = radeon_cs_write_reloc(buf->mgr->rws->cs,
buf->bo, rd, wd, flags);
buf->bo, gem_rd, gem_wd, flags);
if (retval) {
debug_printf("radeon: Relocation of %p (%d, %d, %d) failed!\n",
buf, rd, wd, flags);
buf, gem_rd, gem_wd, flags);
}
}
......
......@@ -173,8 +173,8 @@ static void radeon_set_flush_cb(struct r300_winsys_screen *rws,
static boolean radeon_add_buffer(struct r300_winsys_screen *rws,
struct r300_winsys_buffer *buf,
uint32_t rd,
uint32_t wd)
enum r300_buffer_domain rd,
enum r300_buffer_domain wd)
{
struct pb_buffer *_buf = radeon_pb_buffer(buf);
......@@ -229,8 +229,8 @@ static void radeon_write_cs_table(struct r300_winsys_screen *rws,
static void radeon_write_cs_reloc(struct r300_winsys_screen *rws,
struct r300_winsys_buffer *buf,
uint32_t rd,
uint32_t wd,
enum r300_buffer_domain rd,
enum r300_buffer_domain wd,
uint32_t flags)
{
struct pb_buffer *_buf = radeon_pb_buffer(buf);
......
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