Commit 81dee6cf authored by Bas Nieuwenhuizen's avatar Bas Nieuwenhuizen Committed by Marge Bot

radv: Use offsets in surface struct.

Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <!5194>
parent ffae3589
......@@ -5465,7 +5465,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
if (size != image->planes[0].surface.dcc_size) {
state->flush_bits |=
radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->dcc_offset + size,
image->offset + image->planes[0].surface.dcc_offset + size,
image->planes[0].surface.dcc_size - size,
0xffffffff);
}
......
......@@ -6622,7 +6622,7 @@ radv_initialise_color_surface(struct radv_device *device,
.pipe_aligned = 1,
};
if (iview->image->dcc_offset)
if (surf->dcc_offset)
meta = surf->u.gfx9.dcc;
cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
......@@ -6668,11 +6668,11 @@ radv_initialise_color_surface(struct radv_device *device,
/* CMASK variables */
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->cmask_offset;
va += surf->cmask_offset;
cb->cb_color_cmask = va >> 8;
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->dcc_offset;
va += surf->dcc_offset;
if (radv_dcc_enabled(iview->image, iview->base_mip) &&
device->physical_device->rad_info.chip_class <= GFX8)
......@@ -6697,7 +6697,7 @@ radv_initialise_color_surface(struct radv_device *device,
}
if (radv_image_has_fmask(iview->image)) {
va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
cb->cb_color_fmask = va >> 8;
cb->cb_color_fmask |= surf->fmask_tile_swizzle;
} else {
......@@ -6949,7 +6949,7 @@ radv_initialise_ds_surface(struct radv_device *device,
/* Use all of the htile_buffer for depth if there's no stencil. */
ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
va = radv_buffer_get_va(iview->bo) + iview->image->offset +
iview->image->htile_offset;
surf->htile_offset;
ds->db_htile_data_base = va >> 8;
ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
S_028ABC_PIPE_ALIGNED(1);
......@@ -7017,7 +7017,7 @@ radv_initialise_ds_surface(struct radv_device *device,
ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
va = radv_buffer_get_va(iview->bo) + iview->image->offset +
iview->image->htile_offset;
surf->htile_offset;
ds->db_htile_data_base = va >> 8;
ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
......
......@@ -593,7 +593,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (!disable_compression && radv_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
meta_va = gpu_address + plane->surface.dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
......@@ -602,7 +602,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va |= dcc_tile_swizzle;
} else if (!disable_compression &&
radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
meta_va = gpu_address + plane->surface.htile_offset;
}
if (meta_va) {
......@@ -630,7 +630,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
.pipe_aligned = 1,
};
if (image->dcc_offset)
if (plane->surface.dcc_offset)
meta = plane->surface.u.gfx9.dcc;
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
......@@ -659,7 +659,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
.pipe_aligned = 1,
};
if (image->dcc_offset)
if (plane->surface.dcc_offset)
meta = plane->surface.u.gfx9.dcc;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
......@@ -830,7 +830,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
assert(image->plane_count == 1);
va = gpu_address + image->offset + image->fmask_offset;
va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
switch (image->info.samples) {
case 2:
......@@ -972,7 +972,7 @@ si_make_texture_descriptor(struct radv_device *device,
state[4] |= S_008F20_DEPTH(depth - 1);
state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
if (image->dcc_offset) {
if (image->planes[0].surface.dcc_offset) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
} else {
/* The last dword is unused by hw. The shader uses it to clear
......@@ -994,7 +994,7 @@ si_make_texture_descriptor(struct radv_device *device,
assert(image->plane_count == 1);
va = gpu_address + image->offset + image->fmask_offset;
va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
if (device->physical_device->rad_info.chip_class == GFX9) {
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
......@@ -1054,7 +1054,7 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F24_META_RB_ALIGNED(1);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask_offset;
va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
......@@ -1067,7 +1067,7 @@ si_make_texture_descriptor(struct radv_device *device,
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask_offset;
va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[7] |= va >> 8;
......@@ -1146,7 +1146,7 @@ radv_query_opaque_metadata(struct radv_device *device,
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
desc[1] &= C_008F14_BASE_ADDRESS_HI;
desc[7] = image->dcc_offset >> 8;
desc[7] = image->planes[0].surface.dcc_offset >> 8;
/* Dwords [2:9] contain the image descriptor. */
memcpy(&md->metadata[2], desc, sizeof(desc));
......@@ -1205,8 +1205,8 @@ radv_image_alloc_fmask(struct radv_device *device,
{
unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
image->fmask_offset = align64(image->size, fmask_alignment);
image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
image->planes[0].surface.fmask_offset = align64(image->size, fmask_alignment);
image->size = image->planes[0].surface.fmask_offset + image->planes[0].surface.fmask_size;
image->alignment = MAX2(image->alignment, fmask_alignment);
}
......@@ -1223,13 +1223,13 @@ radv_image_alloc_cmask(struct radv_device *device,
assert(cmask_alignment);
image->cmask_offset = align64(image->size, cmask_alignment);
image->planes[0].surface.cmask_offset = align64(image->size, cmask_alignment);
/* + 8 for storing the clear values */
if (!image->clear_value_offset) {
image->clear_value_offset = image->cmask_offset + cmask_size;
image->clear_value_offset = image->planes[0].surface.cmask_offset + cmask_size;
clear_value_size = 8;
}
image->size = image->cmask_offset + cmask_size + clear_value_size;
image->size = image->planes[0].surface.cmask_offset + cmask_size + clear_value_size;
image->alignment = MAX2(image->alignment, cmask_alignment);
}
......@@ -1238,22 +1238,22 @@ radv_image_alloc_dcc(struct radv_image *image)
{
assert(image->plane_count == 1);
image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
image->planes[0].surface.dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
/* + 24 for storing the clear values + fce pred + dcc pred for each mip */
image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
image->clear_value_offset = image->planes[0].surface.dcc_offset + image->planes[0].surface.dcc_size;
image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
image->size = image->planes[0].surface.dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
}
static void
radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
{
image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
image->planes[0].surface.htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
/* + 8 for storing the clear values */
image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
image->clear_value_offset = image->planes[0].surface.htile_offset + image->planes[0].surface.htile_size;
image->size = image->clear_value_offset + image->info.levels * 8;
if (radv_image_is_tc_compat_htile(image) &&
device->physical_device->rad_info.has_tc_compat_zrange_bug) {
......
......@@ -1481,7 +1481,7 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
uint64_t offset = image->offset + image->cmask_offset;
uint64_t offset = image->offset + image->planes[0].surface.cmask_offset;
uint64_t size;
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
......@@ -1504,7 +1504,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
uint64_t offset = image->offset + image->fmask_offset;
uint64_t offset = image->offset + image->planes[0].surface.fmask_offset;
uint64_t size;
/* MSAA images do not support mipmap levels. */
......@@ -1538,7 +1538,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
radv_update_dcc_metadata(cmd_buffer, image, range, true);
for (uint32_t l = 0; l < level_count; l++) {
uint64_t offset = image->offset + image->dcc_offset;
uint64_t offset = image->offset + image->planes[0].surface.dcc_offset;
uint32_t level = range->baseMipLevel + l;
uint64_t size;
......@@ -1576,7 +1576,7 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
{
unsigned layer_count = radv_get_layerCount(image, range);
uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
uint64_t offset = image->offset + image->htile_offset +
uint64_t offset = image->offset + image->planes[0].surface.htile_offset +
image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
uint32_t htile_mask, flush_bits;
......
......@@ -1804,13 +1804,9 @@ struct radv_image {
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
uint64_t dcc_offset;
uint64_t htile_offset;
bool tc_compatible_htile;
bool tc_compatible_cmask;
uint64_t cmask_offset;
uint64_t fmask_offset;
uint64_t clear_value_offset;
uint64_t fce_pred_offset;
uint64_t dcc_pred_offset;
......@@ -1858,7 +1854,7 @@ bool radv_layout_dcc_compressed(const struct radv_device *device,
static inline bool
radv_image_has_cmask(const struct radv_image *image)
{
return image->cmask_offset;
return image->planes[0].surface.cmask_offset;
}
/**
......@@ -1867,7 +1863,7 @@ radv_image_has_cmask(const struct radv_image *image)
static inline bool
radv_image_has_fmask(const struct radv_image *image)
{
return image->fmask_offset;
return image->planes[0].surface.fmask_offset;
}
/**
......
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