Commit 78cdf9a9 authored by Marek Olšák's avatar Marek Olšák
Browse files

amd/addrlib: add gfx10 support


Acked-by: Bas Nieuwenhuizen's avatarBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
parent 112bf7f9
......@@ -23,6 +23,10 @@ ADDRLIB_FILES = \
addrlib/src/core/coord.h \
addrlib/src/gfx9/gfx9addrlib.cpp \
addrlib/src/gfx9/gfx9addrlib.h \
addrlib/src/gfx10/gfx10addrlib.cpp \
addrlib/src/gfx10/gfx10addrlib.h \
addrlib/src/gfx10/gfx10SwizzlePattern.h \
addrlib/src/chip/gfx10/gfx10_gb_reg.h \
addrlib/src/chip/gfx9/gfx9_gb_reg.h \
addrlib/src/chip/r800/si_gb_reg.h \
addrlib/src/r800/ciaddrlib.cpp \
......
......@@ -2266,17 +2266,17 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
/**
****************************************************************************************************
* ADDR_GET_MAX_ALINGMENTS_OUTPUT
* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
*
* @brief
* Output structure of AddrGetMaxAlignments
****************************************************************************************************
*/
typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_32 baseAlign; ///< Maximum base alignment in bytes
} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;
/**
****************************************************************************************************
......@@ -2288,7 +2288,7 @@ typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
ADDR_HANDLE hLib,
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
/**
****************************************************************************************************
......@@ -2300,7 +2300,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
ADDR_HANDLE hLib,
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
/**
****************************************************************************************************
......
......@@ -37,7 +37,11 @@ files_addrlib = files(
'src/core/coord.h',
'src/gfx9/gfx9addrlib.cpp',
'src/gfx9/gfx9addrlib.h',
'src/gfx10/gfx10addrlib.cpp',
'src/gfx10/gfx10addrlib.h',
'src/gfx10/gfx10SwizzlePattern.h',
'src/amdgpu_asic_addr.h',
'src/chip/gfx10/gfx10_gb_reg.h',
'src/chip/gfx9/gfx9_gb_reg.h',
'src/chip/r800/si_gb_reg.h',
'src/r800/ciaddrlib.cpp',
......@@ -54,8 +58,9 @@ libamdgpu_addrlib = static_library(
include_directories : [
include_directories(
'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
'src/chip/gfx10',
),
inc_amd_common, inc_common, inc_src,
],
cpp_args : cpp_vis_args,
cpp_args : [cpp_vis_args, '-Wno-unused-variable'],
)
......@@ -1070,7 +1070,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
ADDR_HANDLE hLib, ///< address lib handle
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
{
Addr::Lib* pLib = Lib::GetLib(hLib);
......@@ -1101,7 +1101,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
ADDR_HANDLE hLib, ///< address lib handle
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
{
Addr::Lib* pLib = Lib::GetLib(hLib);
......
......@@ -43,6 +43,7 @@
#define FAMILY_CZ 0x87
#define FAMILY_AI 0x8D
#define FAMILY_RV 0x8E
#define FAMILY_NV 0x8F
// AMDGPU_FAMILY_IS(familyId, familyName)
#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
......@@ -55,6 +56,7 @@
#define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ)
#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
#define AMDGPU_UNKNOWN 0xFF
......@@ -92,6 +94,8 @@
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
#define AMDGPU_NAVI10_RANGE 0x01, 0xFF
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
......@@ -134,4 +138,6 @@
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
#endif // _AMDGPU_ASIC_ADDR_H
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#if !defined (__GFX10_GB_REG_H__)
#define __GFX10_GB_REG_H__
/*
* gfx10_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#include "util/u_endian.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
#define LITTLEENDIAN_CPU
#elif defined(PIPE_ARCH_BIG_ENDIAN)
#define BIGENDIAN_CPU
#endif
union GB_ADDR_CONFIG
{
struct
{
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int NUM_PKRS : 3;
unsigned int : 21;
#elif defined(BIGENDIAN_CPU)
unsigned int : 21;
unsigned int NUM_PKRS : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
int i32All;
float f32All;
};
#endif
#if !defined (__GFX9_GB_REG_H__)
#define __GFX9_GB_REG_H__
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
......@@ -27,6 +24,19 @@
* of the Software.
*/
#if !defined (__GFX9_GB_REG_H__)
#define __GFX9_GB_REG_H__
/*
* gfx9_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#include "util/u_endian.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
......@@ -35,15 +45,6 @@
#define BIGENDIAN_CPU
#endif
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG {
struct {
#if defined(LITTLEENDIAN_CPU)
......
#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
......@@ -27,6 +24,20 @@
* of the Software.
*/
#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__
/*****************************************************************************************************************
*
* si_gb_reg.h
*
* Register Spec Release: Chip Spec 0.28
*
*****************************************************************************************************************/
//
// Make sure the necessary endian defines are there.
//
#include "util/u_endian.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
......@@ -35,15 +46,6 @@
#define BIGENDIAN_CPU
#endif
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
/*
* GB_ADDR_CONFIG struct
*/
......
......@@ -241,6 +241,7 @@ enum ChipFamily
ADDR_CHIP_FAMILY_CI,
ADDR_CHIP_FAMILY_VI,
ADDR_CHIP_FAMILY_AI,
ADDR_CHIP_FAMILY_NAVI,
};
/**
......
......@@ -223,6 +223,9 @@ ADDR_E_RETURNCODE Lib::Create(
case FAMILY_RV:
pLib = Gfx9HwlInit(&client);
break;
case FAMILY_NV:
pLib = Gfx10HwlInit(&client);
break;
default:
ADDR_ASSERT_ALWAYS();
break;
......@@ -384,14 +387,14 @@ Lib* Lib::GetLib(
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetMaxAlignments(
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
......@@ -424,14 +427,14 @@ ADDR_E_RETURNCODE Lib::GetMaxAlignments(
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetMaxMetaAlignments(
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
......
......@@ -282,9 +282,9 @@ public:
BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
UINT_32 GetBpe(AddrFormat format) const;
......@@ -409,6 +409,7 @@ private:
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
Lib* Gfx9HwlInit (const Client* pClient);
Lib* Gfx10HwlInit(const Client* pClient);
} // Addr
#endif
......@@ -104,6 +104,8 @@ enum AddrBlockSet
AddrBlockSetLinear = 1 << AddrBlockLinear,
AddrBlockSetMacro = AddrBlockSetMacro4KB | AddrBlockSetMacro64KB,
AddrBlockSet2dGfx10 = AddrBlockSetMicro | AddrBlockSetMacro,
AddrBlockSet3dGfx10 = AddrBlockSetMacro,
};
enum AddrSwSet
......@@ -114,6 +116,8 @@ enum AddrSwSet
AddrSwSetR = 1 << ADDR_SW_R,
AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
AddrSwSet3dThinGfx10 = AddrSwSetZ | AddrSwSetR,
AddrSwSetColorGfx10 = AddrSwSetS | AddrSwSetD | AddrSwSetR,
};
/**
......
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
......
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......@@ -62,6 +62,7 @@ struct Gfx9ChipSettings
// Display engine IP version name
UINT_32 isDce12 : 1;
UINT_32 isDcn1 : 1;
UINT_32 reserved1 : 30;
// Misc configuration bits
UINT_32 metaBaseAlignFix : 1;
......
......@@ -23,7 +23,6 @@
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file egbaddrlib.cpp
......
......@@ -68,7 +68,7 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
......
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