Commit 6010d7b8 authored by Karol Herbst's avatar Karol Herbst 🐧 Committed by Ilia Mirkin

gallium: add PIPE_CAP_MAX_VARYINGS

Some NVIDIA hardware can accept 128 fragment shader input components,
but only have up to 124 varying-interpolated input components. We add a
new cap to express this cleanly. For most drivers, this will have the
same value as PIPE_SHADER_CAP_MAX_INPUTS for the fragment shader.

Fixes KHR-GL45.limits.max_fragment_input_components
Signed-off-by: Karol Herbst's avatarKarol Herbst <karolherbst@gmail.com>
[imirkin: rebased, improved docs/commit message]
Signed-off-by: Ilia Mirkin's avatarIlia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
Acked-by: Eric Anholt's avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
parent 738346fa
......@@ -488,6 +488,10 @@ The integer capabilities:
supports switching the format between sRGB and linear for a surface that is
used as destination in draw and blit calls.
* ``PIPE_CAP_NIR_COMPACT_ARRAYS``: True if the compiler backend supports NIR's compact array feature, for all shader stages.
* ``PIPE_CAP_MAX_VARYINGS``: The maximum number of fragment shader
varyings. This will generally correspond to
``PIPE_SHADER_CAP_MAX_INPUTS`` for the fragment shader, but in some
cases may be a smaller number.
.. _pipe_capf:
......
......@@ -360,6 +360,9 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return 0;
case PIPE_CAP_MAX_VARYINGS:
return screen->specs.max_varyings;
case PIPE_CAP_PCI_GROUP:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
......
......@@ -317,6 +317,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_VIEWPORTS:
return 1;
case PIPE_CAP_MAX_VARYINGS:
return 16;
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
/* manage the variants for these ourself, to avoid breaking precompile: */
......
......@@ -402,6 +402,8 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
return 0;
case PIPE_CAP_ENDIANNESS:
return PIPE_ENDIAN_LITTLE;
case PIPE_CAP_MAX_VARYINGS:
return 10;
case PIPE_CAP_VENDOR_ID:
return 0x8086;
......
......@@ -310,6 +310,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 1;
case PIPE_CAP_CLEAR_TEXTURE:
return 1;
case PIPE_CAP_MAX_VARYINGS:
return 32;
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
......
......@@ -79,6 +79,9 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 2048;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 8 * 1024 * 1024;
case PIPE_CAP_MAX_VARYINGS:
return 8;
/* supported capabilities */
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
......
......@@ -156,6 +156,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return NV50_MAX_WINDOW_RECTANGLES;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 16 * 1024 * 1024;
case PIPE_CAP_MAX_VARYINGS:
return 15;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
......
......@@ -182,6 +182,13 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return class_3d >= GM200_3D_CLASS ? 8 : 0;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 64 * 1024 * 1024;
case PIPE_CAP_MAX_VARYINGS:
/* NOTE: These only count our slots for GENERIC varyings.
* The address space may be larger, but the actual hard limit seems to be
* less than what the address space layout permits, so don't add TEXCOORD,
* COLOR, etc. here.
*/
return 0x1f0 / 16;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
......@@ -394,18 +401,6 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 16;
case PIPE_SHADER_CAP_MAX_INPUTS:
if (shader == PIPE_SHADER_VERTEX)
return 32;
/* NOTE: These only count our slots for GENERIC varyings.
* The address space may be larger, but the actual hard limit seems to be
* less than what the address space layout permits, so don't add TEXCOORD,
* COLOR, etc. here.
*/
if (shader == PIPE_SHADER_FRAGMENT)
return 0x1f0 / 16;
/* Actually this counts CLIPVERTEX, which occupies the last generic slot,
* and excludes 0x60 per-patch inputs.
*/
return 0x200 / 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 32;
......
......@@ -250,6 +250,9 @@ panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_MAX_VARYINGS:
return 16;
default:
return u_pipe_screen_get_param_defaults(screen, param);
}
......
......@@ -304,6 +304,9 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
case PIPE_CAP_MAX_VARYINGS:
return 10;
case PIPE_CAP_VENDOR_ID:
return 0x1002;
case PIPE_CAP_DEVICE_ID:
......
......@@ -536,6 +536,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
case PIPE_CAP_MAX_VARYINGS:
return 32;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
case PIPE_CAP_ENDIANNESS:
......
......@@ -254,6 +254,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 30;
case PIPE_CAP_MAX_VARYINGS:
return 32;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return sscreen->info.chip_class <= VI ?
PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
......
......@@ -265,6 +265,8 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 1;
case PIPE_CAP_CLEAR_TEXTURE:
return 1;
case PIPE_CAP_MAX_VARYINGS:
return TGSI_EXEC_MAX_INPUT_ATTRIBS;
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
......
......@@ -350,6 +350,8 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return sws->have_sm4_1 ? 1 : 0; /* only single-channel textures */
case PIPE_CAP_MAX_VARYINGS:
return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS : 10;
/* Unsupported features */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
......
......@@ -177,6 +177,9 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return 4;
case PIPE_CAP_MAX_VARYINGS:
return V3D_MAX_FS_INPUTS / 4;
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
......
......@@ -178,6 +178,9 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
/* Note: Not supported in hardware, just faking it. */
return 5;
case PIPE_CAP_MAX_VARYINGS:
return 8;
case PIPE_CAP_VENDOR_ID:
return 0x14E4;
case PIPE_CAP_ACCELERATED:
......
......@@ -260,6 +260,10 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 1; /* TODO: need to introduce a hw-cap for this */
case PIPE_CAP_QUERY_BUFFER_OBJECT:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
case PIPE_CAP_MAX_VARYINGS:
if (vscreen->caps.caps.v1.glsl_level < 150)
return vscreen->caps.caps.v2.max_vertex_attribs;
return 32;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
......
......@@ -857,6 +857,7 @@ enum pipe_cap
PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
PIPE_CAP_NIR_COMPACT_ARRAYS,
PIPE_CAP_MAX_VARYINGS,
};
/**
......
......@@ -365,10 +365,7 @@ void st_init_limits(struct pipe_screen *screen,
c->Program[MESA_SHADER_VERTEX].MaxAttribs =
MIN2(c->Program[MESA_SHADER_VERTEX].MaxAttribs, 16);
/* PIPE_SHADER_CAP_MAX_INPUTS for the FS specifies the maximum number
* of inputs. It's always 2 colors + N generic inputs. */
c->MaxVarying = screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
PIPE_SHADER_CAP_MAX_INPUTS);
c->MaxVarying = screen->get_param(screen, PIPE_CAP_MAX_VARYINGS);
c->MaxVarying = MIN2(c->MaxVarying, MAX_VARYING);
c->MaxGeometryOutputVertices =
screen->get_param(screen, PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES);
......
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