Commit 361b3fee authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by Marge Bot
Browse files

intel: move away from booleans to identify platforms



v2: Drop changes around GFX_VERx10 == 75 (Luis)

v3: Replace
   (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
   by
   (devinfo->platform == INTEL_PLATFORM_IVB)
   Replace
   (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 >= 45)
   Replace
   (devinfo->platform != INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 != 45)

v4: Fix crocus typo

v5: Rebase

v6: Add GFX3, ILK & I965 platforms (Jordan)
    Move ifdef to code expressions (Jordan)
Signed-off-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen's avatarJordan Justen <jordan.l.justen@intel.com>
Part-of: <!12981>
parent 3b1a5b8f
......@@ -67,7 +67,7 @@
* or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
* need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
*/
#define BATCH_RESERVED(devinfo) ((devinfo)->is_haswell ? 32 : 16)
#define BATCH_RESERVED(devinfo) ((devinfo)->platform == INTEL_PLATFORM_HSW ? 32 : 16)
static void crocus_batch_reset(struct crocus_batch *batch);
......
......@@ -189,7 +189,7 @@ crocus_emit_end_of_pipe_sync(struct crocus_batch *batch,
batch->ice->workaround_bo,
batch->ice->workaround_offset, 0);
if (batch->screen->devinfo.is_haswell) {
if (batch->screen->devinfo.platform == INTEL_PLATFORM_HSW) {
#define GEN7_3DPRIM_START_INSTANCE 0x243C
batch->screen->vtbl.load_register_mem32(batch, GEN7_3DPRIM_START_INSTANCE,
batch->ice->workaround_bo,
......
......@@ -734,7 +734,7 @@ crocus_screen_create(int fd, const struct pipe_screen_config *config)
if (screen->devinfo.ver == 8) {
/* bind to cherryview or bdw if forced */
if (!screen->devinfo.is_cherryview &&
if (screen->devinfo.platform != INTEL_PLATFORM_CHV &&
!getenv("CROCUS_GEN8"))
return NULL;
}
......
......@@ -1125,11 +1125,11 @@ setup_l3_config(struct crocus_batch *batch, const struct intel_l3_config *cfg)
* client (URB for all validated configurations) set to the
* lower-bandwidth 2-bank address hashing mode.
*/
const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
const bool urb_low_bw = has_slm && devinfo->platform != INTEL_PLATFORM_BYT;
assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
/* Minimum number of ways that can be allocated to the URB. */
const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
const unsigned n0_urb = (devinfo->platform == INTEL_PLATFORM_BYT ? 32 : 0);
assert(cfg->n[INTEL_L3P_URB] >= n0_urb);
uint32_t l3sqcr1, l3cr2, l3cr3;
......@@ -1143,7 +1143,7 @@ setup_l3_config(struct crocus_batch *batch, const struct intel_l3_config *cfg)
reg.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT;
#else
reg.L3SQGeneralPriorityCreditInitialization =
devinfo->is_baytrail ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT;
devinfo->platform == INTEL_PLATFORM_BYT ? BYT_SQGPCI_DEFAULT : SQGPCI_DEFAULT;
#endif
reg.L3SQHighPriorityCreditInitialization = SQHPCI_DEFAULT;
};
......@@ -1348,7 +1348,7 @@ crocus_alloc_push_constants(struct crocus_batch *batch)
*
* No such restriction exists for Haswell or Baytrail.
*/
if (!(GFX_VERx10 == 75) && !batch->screen->devinfo.is_baytrail)
if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB)
gen7_emit_cs_stall_flush(batch);
}
#endif
......@@ -2025,7 +2025,7 @@ crocus_create_rasterizer_state(struct pipe_context *ctx,
#endif
#if GFX_VER == 8
struct crocus_screen *screen = (struct crocus_screen *)ctx->screen;
if (screen->devinfo.is_cherryview)
if (screen->devinfo.platform == INTEL_PLATFORM_CHV)
sf.CHVLineWidth = line_width;
else
sf.LineWidth = line_width;
......@@ -3663,7 +3663,7 @@ crocus_set_vertex_buffers(struct pipe_context *ctx,
struct crocus_context *ice = (struct crocus_context *) ctx;
struct crocus_screen *screen = (struct crocus_screen *) ctx->screen;
const unsigned padding =
(GFX_VERx10 < 75 && !screen->devinfo.is_baytrail) * 2;
(GFX_VERx10 < 75 && screen->devinfo.platform != INTEL_PLATFORM_BYT) * 2;
ice->state.bound_vertex_buffers &=
~u_bit_consecutive64(start_slot, count + unbind_num_trailing_slots);
......@@ -5704,7 +5704,7 @@ emit_push_constant_packets(struct crocus_context *ice,
#if GFX_VER == 7
if (stage == MESA_SHADER_VERTEX) {
if (!(GFX_VERx10 == 75) && !batch->screen->devinfo.is_baytrail)
if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB)
gen7_emit_vs_workaround_flush(batch);
}
#endif
......@@ -6088,7 +6088,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice,
entries, start, NULL, &constrained);
#if GFX_VER == 7
if (GFX_VERx10 < 75 && !devinfo->is_baytrail)
if (devinfo->platform == INTEL_PLATFORM_IVB)
gen7_emit_vs_workaround_flush(batch);
#endif
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
......@@ -6731,7 +6731,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice,
const struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(shader->prog_data);
const struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
#if GFX_VER == 7
if (batch->screen->devinfo.is_ivybridge)
if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB)
gen7_emit_vs_workaround_flush(batch);
#endif
......
......@@ -785,7 +785,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
p_atomic_set(&screen->refcount, 1);
if (screen->devinfo.ver < 8 || screen->devinfo.is_cherryview)
if (screen->devinfo.ver < 8 || screen->devinfo.platform == INTEL_PLATFORM_CHV)
return NULL;
driParseConfigFiles(config->options, config->options_info, 0, "iris",
......
......@@ -1011,7 +1011,7 @@ iris_init_render_context(struct iris_batch *batch)
reg.PartialResolveDisableInVCMask = true;
}
if (devinfo->is_geminilake)
if (devinfo->platform == INTEL_PLATFORM_GLK)
init_glk_barrier_mode(batch, GLK_BARRIER_MODE_3D_HULL);
#endif
......@@ -1112,7 +1112,7 @@ iris_init_compute_context(struct iris_batch *batch)
#endif
#if GFX_VER == 9
if (devinfo->is_geminilake)
if (devinfo->platform == INTEL_PLATFORM_GLK)
init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU);
#endif
......
......@@ -165,10 +165,10 @@ get_l3_list(const struct intel_device_info *devinfo)
{
switch (devinfo->ver) {
case 7:
return (devinfo->is_baytrail ? &vlv_l3_list : &ivb_l3_list);
return (devinfo->platform == INTEL_PLATFORM_BYT ? &vlv_l3_list : &ivb_l3_list);
case 8:
return (devinfo->is_cherryview ? &chv_l3_list : &bdw_l3_list);
return (devinfo->platform == INTEL_PLATFORM_CHV ? &chv_l3_list : &bdw_l3_list);
case 9:
if (devinfo->l3_banks == 1)
......@@ -179,7 +179,8 @@ get_l3_list(const struct intel_device_info *devinfo)
return &icl_l3_list;
case 12:
if (devinfo->is_dg1 || devinfo->is_dg2)
if (devinfo->platform == INTEL_PLATFORM_DG1 ||
devinfo->platform == INTEL_PLATFORM_DG2)
return &empty_l3_list;
else
return &tgl_l3_list;
......@@ -269,7 +270,7 @@ intel_get_default_l3_weights(const struct intel_device_info *devinfo,
w.w[INTEL_L3P_ALL] = 1.0;
} else {
w.w[INTEL_L3P_DC] = needs_dc ? 0.1 : 0;
w.w[INTEL_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
w.w[INTEL_L3P_RO] = devinfo->platform == INTEL_PLATFORM_BYT ? 0.5 : 1.0;
}
return norm_l3_weights(w);
......@@ -352,7 +353,7 @@ intel_get_l3_config_urb_size(const struct intel_device_info *devinfo,
const struct intel_l3_config *cfg)
{
/* We don't have to program the URB size in DG1, it's a fixed value. */
if (devinfo->is_dg1)
if (devinfo->platform == INTEL_PLATFORM_DG1)
return devinfo->urb.size;
/* From the SKL "L3 Allocation and Programming" documentation:
......
......@@ -194,7 +194,8 @@ mi_builder_test::SetUp()
(void *)&getparam), 0) << strerror(errno);
ASSERT_TRUE(intel_get_device_info_from_pci_id(device_id, &devinfo));
if (devinfo.ver != GFX_VER || devinfo.is_haswell != (GFX_VERx10 == 75)) {
if (devinfo.ver != GFX_VER ||
(devinfo.platform == INTEL_PLATFORM_HSW) != (GFX_VERx10 == 75)) {
close(fd);
fd = -1;
continue;
......
......@@ -424,7 +424,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
/* Rearrange userclip outcodes so that they come directly after
* the fixed plane bits.
*/
if (p->devinfo->ver == 5 || p->devinfo->is_g4x)
if (p->devinfo->ver == 5 || p->devinfo->verx10 == 45)
brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
else
brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
......
......@@ -2100,7 +2100,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
brw_sampler_desc_binding_table_index(devinfo, imm_desc),
brw_sampler_desc_sampler(devinfo, imm_desc),
brw_sampler_desc_msg_type(devinfo, imm_desc));
if (!devinfo->is_g4x) {
if (devinfo->verx10 != 45) {
err |= control(file, "sampler target format",
sampler_target_format,
brw_sampler_desc_return_format(devinfo, imm_desc),
......@@ -2120,7 +2120,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
devinfo->ver >= 7 ? 0u :
brw_dp_write_desc_write_commit(devinfo, imm_desc));
} else {
bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x;
bool is_965 = devinfo->verx10 == 40;
err |= control(file, "DP read message type",
is_965 ? gfx4_dp_read_port_msg_type :
g45_dp_read_port_msg_type,
......
......@@ -402,7 +402,7 @@ brw_sampler_desc(const struct intel_device_info *devinfo,
else if (devinfo->ver >= 5)
return (desc | SET_BITS(msg_type, 15, 12) |
SET_BITS(simd_mode, 17, 16));
else if (devinfo->is_g4x)
else if (devinfo->verx10 >= 45)
return desc | SET_BITS(msg_type, 15, 12);
else
return (desc | SET_BITS(return_format, 13, 12) |
......@@ -429,7 +429,7 @@ brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc
{
if (devinfo->ver >= 7)
return GET_BITS(desc, 16, 12);
else if (devinfo->ver >= 5 || devinfo->is_g4x)
else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 15, 12);
else
return GET_BITS(desc, 15, 14);
......@@ -450,7 +450,7 @@ static inline unsigned
brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->ver == 4 && !devinfo->is_g4x);
assert(devinfo->verx10 == 40);
return GET_BITS(desc, 13, 12);
}
......@@ -522,7 +522,7 @@ brw_dp_read_desc(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 6)
return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
else if (devinfo->ver >= 5 || devinfo->is_g4x)
else if (devinfo->verx10 >= 45)
return (SET_BITS(binding_table_index, 7, 0) |
SET_BITS(msg_control, 10, 8) |
SET_BITS(msg_type, 13, 11) |
......@@ -540,7 +540,7 @@ brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 6)
return brw_dp_desc_msg_type(devinfo, desc);
else if (devinfo->ver >= 5 || devinfo->is_g4x)
else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 13, 11);
else
return GET_BITS(desc, 13, 12);
......@@ -552,7 +552,7 @@ brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo,
{
if (devinfo->ver >= 6)
return brw_dp_desc_msg_control(devinfo, desc);
else if (devinfo->ver >= 5 || devinfo->is_g4x)
else if (devinfo->verx10 >= 45)
return GET_BITS(desc, 10, 8);
else
return GET_BITS(desc, 11, 8);
......@@ -779,7 +779,7 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo,
} else {
if (devinfo->ver >= 7) {
msg_type = GFX7_DATAPORT_DC_DWORD_SCATTERED_READ;
} else if (devinfo->ver > 4 || devinfo->is_g4x) {
} else if (devinfo->verx10 >= 45) {
msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
} else {
msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
......
......@@ -1331,7 +1331,7 @@ set_3src_control_index(const struct intel_device_info *devinfo,
(brw_inst_bits(src, 34, 32) << 21) | /* 3b */
(brw_inst_bits(src, 28, 8)); /* 21b */
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
uncompacted |=
brw_inst_bits(src, 36, 35) << 24; /* 2b */
}
......@@ -1392,7 +1392,7 @@ set_3src_source_index(const struct intel_device_info *devinfo,
(brw_inst_bits(src, 72, 65) << 19) | /* 8b */
(brw_inst_bits(src, 55, 37)); /* 19b */
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
uncompacted |=
(brw_inst_bits(src, 126, 125) << 47) | /* 2b */
(brw_inst_bits(src, 105, 104) << 45) | /* 2b */
......@@ -1480,7 +1480,7 @@ has_3src_unmapped_bits(const struct intel_device_info *devinfo,
*/
if (devinfo->ver >= 12) {
assert(!brw_inst_bits(src, 7, 7));
} else if (devinfo->ver >= 9 || devinfo->is_cherryview) {
} else if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
assert(!brw_inst_bits(src, 127, 127) &&
!brw_inst_bits(src, 7, 7));
} else {
......@@ -1728,7 +1728,7 @@ precompact(const struct intel_device_info *devinfo, brw_inst inst)
* immediate we set.
*/
if (devinfo->ver >= 6 &&
!(devinfo->is_haswell &&
!(devinfo->platform == INTEL_PLATFORM_HSW &&
brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) &&
!(devinfo->ver >= 8 &&
(brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
......@@ -2082,7 +2082,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c,
brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7);
brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff);
if (devinfo->ver >= 9 || devinfo->is_cherryview)
if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV)
brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3);
}
}
......@@ -2125,7 +2125,7 @@ set_uncompacted_3src_source_index(const struct intel_device_info *devinfo,
brw_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff);
brw_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff);
if (devinfo->ver >= 9 || devinfo->is_cherryview) {
if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3);
brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3);
brw_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1);
......@@ -2339,13 +2339,13 @@ static void
update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
assert(devinfo->ver == 5 || devinfo->is_g4x);
assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X);
/* Jump Count is in units of:
* - uncompacted instructions on G45; and
* - compacted instructions on Gfx5.
*/
int shift = devinfo->is_g4x ? 1 : 0;
int shift = devinfo->platform == INTEL_PLATFORM_G4X ? 1 : 0;
int jump_count_compacted = brw_inst_gfx4_jump_count(devinfo, insn) << shift;
......@@ -2462,7 +2462,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
*/
int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1];
if (devinfo->ver == 4 && !devinfo->is_g4x)
if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X)
return;
struct compaction_state c;
......@@ -2495,7 +2495,8 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
offset += sizeof(brw_compact_inst);
} else {
/* All uncompacted instructions need to be aligned on G45. */
if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
if ((offset & sizeof(brw_compact_inst)) != 0 &&
devinfo->platform == INTEL_PLATFORM_G4X) {
brw_compact_inst *align = store + offset;
memset(align, 0, sizeof(*align));
brw_compact_inst_set_hw_opcode(
......
......@@ -3544,7 +3544,7 @@ brw_broadcast(struct brw_codegen *p,
/* Use indirect addressing to fetch the specified component. */
if (type_sz(src.type) > 4 &&
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
(devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
*
......
......@@ -862,7 +862,8 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
ERROR_IF(subreg % 4 != 0,
"Conversions between integer and half-float must be "
"aligned to a DWord on the destination");
} else if ((devinfo->is_cherryview || devinfo->ver >= 9) &&
} else if ((devinfo->platform == INTEL_PLATFORM_CHV ||
devinfo->ver >= 9) &&
dst_type == BRW_REGISTER_TYPE_HF) {
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
ERROR_IF(dst_stride != 2 &&
......@@ -881,7 +882,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
*/
bool validate_dst_size_and_exec_size_ratio =
!is_mixed_float(devinfo, inst) ||
!(devinfo->is_cherryview || devinfo->ver >= 9);
!(devinfo->platform == INTEL_PLATFORM_CHV || devinfo->ver >= 9);
if (validate_dst_size_and_exec_size_ratio &&
exec_type_size > dst_type_size) {
......@@ -900,7 +901,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
* Implementation Restriction: The relaxed alignment rule for byte
* destination (#10.5) is not supported.
*/
if ((devinfo->ver > 4 || devinfo->is_g4x) && dst_type_is_byte) {
if (devinfo->verx10 >= 45 && dst_type_is_byte) {
ERROR_IF(subreg % exec_type_size != 0 &&
subreg % exec_type_size != 1,
"Destination subreg must be aligned to the size of the "
......@@ -1820,7 +1821,7 @@ special_requirements_for_handling_double_precision_data_types(
*/
if (is_double_precision &&
brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
(devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(!is_scalar_region &&
(src_stride % 8 != 0 ||
dst_stride % 8 != 0 ||
......@@ -1845,7 +1846,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction applies to GLK as well.
*/
if (is_double_precision &&
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
(devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode ||
BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode,
"Indirect addressing is not allowed when the execution type "
......@@ -1862,7 +1863,8 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction does not apply to the null register.
*/
if (is_double_precision &&
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
(devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo))) {
ERROR_IF(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MAC ||
brw_inst_acc_wr_control(devinfo, inst) ||
(BRW_ARCHITECTURE_REGISTER_FILE == file &&
......@@ -1949,7 +1951,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction applies to GLK as well.
*/
if (is_double_precision &&
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
(devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(brw_inst_no_dd_check(devinfo, inst) ||
brw_inst_no_dd_clear(devinfo, inst),
"DepCtrl is not allowed when the execution type is 64-bit");
......
......@@ -3829,7 +3829,7 @@ fs_visitor::insert_gfx4_post_send_dependency_workarounds(bblock_t *block, fs_ins
void
fs_visitor::insert_gfx4_send_dependency_workarounds()
{
if (devinfo->ver != 4 || devinfo->is_g4x)
if (devinfo->ver != 4 || devinfo->platform == INTEL_PLATFORM_G4X)
return;
bool progress = false;
......@@ -7105,7 +7105,7 @@ get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
for (unsigned i = 0; i < inst->sources; i++) {
/* IVB implements DF scalars as <0;2,1> regions. */
const bool is_scalar_exception = is_uniform(inst->src[i]) &&
(devinfo->is_haswell || type_sz(inst->src[i].type) != 8);
(devinfo->platform == INTEL_PLATFORM_HSW || type_sz(inst->src[i].type) != 8);
const bool is_packed_word_exception =
type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
......@@ -7384,7 +7384,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
* should
* "Force BFI instructions to be executed always in SIMD8."
*/
return MIN2(devinfo->is_haswell ? 8 : ~0u,
return MIN2(devinfo->platform == INTEL_PLATFORM_HSW ? 8 : ~0u,
get_fpu_lowered_simd_width(devinfo, inst));
case BRW_OPCODE_IF:
......@@ -7401,7 +7401,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
/* Unary extended math instructions are limited to SIMD8 on Gfx4 and
* Gfx6. Extended Math Function is limited to SIMD8 with half-float.
*/
if (devinfo->ver == 6 || (devinfo->ver == 4 && !devinfo->is_g4x))
if (devinfo->ver == 6 || devinfo->verx10 == 40)
return MIN2(8, inst->exec_size);
if (inst->dst.type == BRW_REGISTER_TYPE_HF)
return MIN2(8, inst->exec_size);
......@@ -8937,7 +8937,7 @@ fs_visitor::allocate_registers(bool allow_spilling)
prog_data->total_scratch = brw_get_scratch_size(last_scratch);
if (stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) {
if (devinfo->is_haswell) {
if (devinfo->platform == INTEL_PLATFORM_HSW) {
/* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
* field documentation, Haswell supports a minimum of 2kB of
* scratch space for compute shaders, unlike every other stage
......@@ -9328,7 +9328,7 @@ fs_visitor::run_cs(bool allow_spilling)
if (shader_time_index >= 0)
emit_shader_time_begin();
if (devinfo->is_haswell && prog_data->total_shared > 0) {
if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) {
/* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
const fs_builder abld = bld.exec_all().group(1, 0);
abld.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW),
......
......@@ -279,7 +279,7 @@ fs_generator::patch_halt_jumps()
brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH);
}
if (devinfo->ver == 4 && !devinfo->is_g4x) {
if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) {
/* From the g965 PRM:
*
* "[DevBW, DevCL] Erratum: The subfields in mask stack register are
......@@ -550,7 +550,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
if (type_sz(reg.type) > 4 &&
((devinfo->verx10 == 70) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
/* IVB has an issue (which we found empirically) where it reads two
* address register components per channel for indirectly addressed
......@@ -715,7 +715,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
if (type_sz(src.type) > 4 &&
((devinfo->verx10 == 70) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly
......@@ -1418,7 +1418,7 @@ fs_generator::generate_ddy(const fs_inst *inst,
* inherits its FP16 hardware from SKL, so it is not affected.
*/
if (devinfo->ver >= 11 ||
(devinfo->is_broadwell && src.type == BRW_REGISTER_TYPE_HF)) {
(devinfo->platform == INTEL_PLATFORM_BDW && src.type == BRW_REGISTER_TYPE_HF)) {
src = stride(src, 0, 2, 1);
brw_push_insn_state(p);
......@@ -2285,7 +2285,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
src[0], brw_null_reg());
} else {
assert(inst->mlen >= 1);
assert(devinfo->ver == 5 || devinfo->is_g4x || inst->exec_size == 8);
assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X || inst->exec_size == 8);
gfx4_math(p, dst,
brw_math_function(inst->opcode),
inst->base_mrf, src[0],
......@@ -2583,7 +2583,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
struct brw_reg strided = stride(suboffset(src[0], component),
vstride, width, 0);
if (type_sz(src[0].type) > 4 &&
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
(devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly
......@@ -2661,7 +2662,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
break;
case BRW_OPCODE_DIM:
assert(devinfo->is_haswell);
assert(devinfo->platform == INTEL_PLATFORM_HSW);
assert(src[0].type == BRW_REGISTER_TYPE_DF);
assert(dst.type == BRW_REGISTER_TYPE_DF);
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
......
......@@ -203,7 +203,8 @@ namespace {
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
return (((devinfo->verx10 == 70) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) ||
(devinfo->verx10 >= 125 &&
brw_reg_type_is_floating_point(inst->src[0].type)) ?
......
......@@ -4658,7 +4658,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
(instr->num_components - 1) * type_sz(dest.type);
bool supports_64bit_indirects =
!devinfo->is_cherryview && !intel_device_info_is_9lp(devinfo);
devinfo->platform != INTEL_PLATFORM_CHV && !intel_device_info_is_9lp(devinfo);
if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
for (unsigned j = 0; j < instr->num_components; j++) {
......@@ -6467,7 +6467,7 @@ setup_imm_df(const fs_builder &bld, double v)
/* gfx7.5 does not support DF immediates straighforward but the DIM
* instruction allows to set the 64-bit immediate value.
*/
if (devinfo->is_haswell) {
if (devinfo->platform == INTEL_PLATFORM_HSW) {
const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1);
ubld.DIM(dst, brw_imm_df(v));
......
......@@ -93,7 +93,7 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
high = hi6; low = lo6; \
} else if (devinfo->ver >= 5) { \
high = hi5; low = lo5; \
} else if (devinfo->is_g4x) { \