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Commit 18a560dd authored by Indrajit Kumar Das's avatar Indrajit Kumar Das Committed by Marek Olšák
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radeonsi/gfx11: VRS changes

parent 6359310f
This commit is part of merge request !16328. Comments created here will be created in the context of that merge request.
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src/gallium/drivers/radeonsi/si_gfx_cs.c
Edit View file @ 18a560dd
......@@ -260,7 +260,7 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_VRS_OVERRIDE_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000;
......
src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
Edit View file @ 18a560dd
......@@ -601,19 +601,30 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx,
}
if (writes_vrs) {
/* Bits [2:3] = VRS rate X
* Bits [4:5] = VRS rate Y
*
* The range is [-2, 1]. Values:
* 1: 2x coarser shading rate in that direction.
* 0: normal shading rate
* -1: 2x finer shading rate (sample shading, not directional)
* -2: 4x finer shading rate (sample shading, not directional)
*
* Sample shading can't go above 8 samples, so both numbers can't be -2
* at the same time.
*/
LLVMValueRef rates = LLVMConstInt(ctx->ac.i32, (1 << 2) | (1 << 4), 0);
LLVMValueRef rates;
if (ctx->screen->info.chip_class >= GFX11) {
/* Bits [2:5] = VRS rate
*
* The range is [0, 15].
*
* If the hw doesn't support VRS 4x4, it will silently use 2x2 instead.
*/
rates = LLVMConstInt(ctx->ac.i32, (V_0283D0_VRS_SHADING_RATE_4X4 << 2), 0);
} else {
/* Bits [2:3] = VRS rate X
* Bits [4:5] = VRS rate Y
*
* The range is [-2, 1]. Values:
* 1: 2x coarser shading rate in that direction.
* 0: normal shading rate
* -1: 2x finer shading rate (sample shading, not directional)
* -2: 4x finer shading rate (sample shading, not directional)
*
* Sample shading can't go above 8 samples, so both numbers can't be -2
* at the same time.
*/
rates = LLVMConstInt(ctx->ac.i32, (1 << 2) | (1 << 4), 0);
}
/* If Pos.W != 1 (typical for non-GUI elements), use 2x2 coarse shading. */
rates = LLVMBuildSelect(ctx->ac.builder,
......
src/gallium/drivers/radeonsi/si_state.c
Edit View file @ 18a560dd
......@@ -1592,28 +1592,48 @@ static void si_emit_db_render_state(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
db_shader_control);
if (sctx->chip_class == GFX10_3) {
if (sctx->chip_class >= GFX10_3) {
if (sctx->allow_flat_shading) {
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(
V_028064_VRS_COMB_MODE_OVERRIDE) |
S_028064_VRS_OVERRIDE_RATE_X(1) |
S_028064_VRS_OVERRIDE_RATE_Y(1));
if (sctx->chip_class == GFX11) {
radeon_opt_set_context_reg(sctx, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
S_0283D0_VRS_OVERRIDE_RATE_COMBINER_MODE(
V_0283D0_SC_VRS_COMB_MODE_OVERRIDE) |
/* If the hw doesn't support VRS 4x4, it will silently
* use 2x2 instead. */
S_0283D0_VRS_RATE(V_0283D0_VRS_SHADING_RATE_4X4));
} else {
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(
V_028064_VRS_COMB_MODE_OVERRIDE) |
S_028064_VRS_OVERRIDE_RATE_X(1) |
S_028064_VRS_OVERRIDE_RATE_Y(1));
}
} else {
/* If the shader is using discard, turn off coarse shading because
* discard at 2x2 pixel granularity degrades quality too much.
*
* MIN allows sample shading but not coarse shading.
*/
unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU;
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
S_028064_VRS_OVERRIDE_RATE_X(0) |
S_028064_VRS_OVERRIDE_RATE_Y(0));
if (sctx->chip_class == GFX11) {
unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
V_0283D0_SC_VRS_COMB_MODE_MIN : V_0283D0_SC_VRS_COMB_MODE_PASSTHRU;
radeon_opt_set_context_reg(sctx, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
S_0283D0_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
S_0283D0_VRS_RATE(V_0283D0_VRS_SHADING_RATE_1X1));
} else {
unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU;
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
S_028064_VRS_OVERRIDE_RATE_X(0) |
S_028064_VRS_OVERRIDE_RATE_Y(0));
}
}
}
radeon_end_update_context_roll(sctx);
......
src/gallium/drivers/radeonsi/si_state.h
Edit View file @ 18a560dd
......@@ -276,7 +276,7 @@ enum si_tracked_reg
SI_TRACKED_PA_SC_BINNER_CNTL_0,
SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
......
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