gallium: remove PIPE_CAP_INFO_START_WITH_USER_INDICES and fix all drivers

Drivers aren't allowed to ignore start with user index buffers anymore.
This is required by the new fast path where mesa/main is using pipe_draw_info.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <!7679>

docs/gallium/screen.rst

@@ -581,7 +581,6 @@ The integer capabilities:
 * ``PIPE_CAP_PACKED_STREAM_OUTPUT``: Driver supports packing optimization for stream output (e.g. GL transform feedback captured variables). Defaults to true.
 * ``PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED``: Driver needs the nir_lower_viewport_transform pass to be enabled. This also means that the gl_Position value is modified and should be lowered for transform feedback, if needed. Defaults to false.
 * ``PIPE_CAP_PSIZ_CLAMPED``: Driver needs for the point size to be clamped. Additionally, the gl_PointSize has been modified and its value should be lowered for transform feedback, if needed. Defaults to false.
-* ``PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES``: pipe_draw_info::start can be non-zero with user indices.
 * ``PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE``: Buffer size used to upload vertices for glBegin/glEnd.
 * ``PIPE_CAP_VIEWPORT_SWIZZLE``: Whether pipe_viewport_state::swizzle can be used to specify pre-clipping swizzling of coordinates (see GL_NV_viewport_swizzle).
 * ``PIPE_CAP_SYSTEM_SVM``: True if all application memory can be shared with the GPU without explicit mapping.

src/gallium/auxiliary/util/u_screen.c

@@ -415,7 +415,6 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
 
    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
    case PIPE_CAP_INTEGER_MULTIPLY_32X16:
-   case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
       return 0;
    case PIPE_CAP_NIR_IMAGES_AS_DEREF:
       return 1;

src/gallium/drivers/iris/iris_state.c

@@ -6447,9 +6447,13 @@ iris_upload_render_state(struct iris_context *ice,
       unsigned offset;
 
       if (draw->has_user_indices) {
-         u_upload_data(ice->ctx.stream_uploader, 0,
-                       sc->count * draw->index_size, 4, draw->index.user,
+         unsigned start_offset = draw->index_size * sc->start;
+
+         u_upload_data(ice->ctx.stream_uploader, start_offset,
+                       sc->count * draw->index_size, 4,
+                       (char*)draw->index.user + start_offset,
                        &offset, &ice->state.last_res.index_buffer);
+         offset -= start_offset;
       } else {
          struct iris_resource *res = (void *) draw->index.resource;
          res->bind_history |= PIPE_BIND_INDEX_BUFFER;

src/gallium/drivers/nouveau/nv30/nv30_push.c

@@ -231,7 +231,7 @@ nv30_push_vbo(struct nv30_context *nv30, const struct pipe_draw_info *info,
             nv04_resource(info->index.resource), draw->start * info->index_size,
             NOUVEAU_BO_RD);
       else
-         ctx.idxbuf = info->index.user;
+         ctx.idxbuf = (char*)info->index.user + draw->start * info->index_size;
       if (!ctx.idxbuf) {
          nv30_state_release(nv30);
          return;

src/gallium/drivers/nouveau/nv30/nv30_vbo.c

@@ -515,7 +515,7 @@ nv30_draw_elements(struct nv30_context *nv30, bool shorten,
                                             nv04_resource(info->index.resource),
                                             start * index_size, NOUVEAU_BO_RD);
       else
-         data = info->index.user;
+         data = (char*)info->index.user + start * index_size;
       if (!data)
          return;
 

src/gallium/drivers/nouveau/nv50/nv50_screen.c

@@ -234,7 +234,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TWO_SIDED_COLOR:
    case PIPE_CAP_CLIP_PLANES:
    case PIPE_CAP_PACKED_STREAM_OUTPUT:
-   case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
       return 1;
    case PIPE_CAP_SEAMLESS_CUBE_MAP:
       return 1; /* class_3d >= NVA0_3D_CLASS; */

src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

@@ -297,7 +297,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_CLIP_PLANES:
    case PIPE_CAP_TEXTURE_SHADOW_LOD:
    case PIPE_CAP_PACKED_STREAM_OUTPUT:
-   case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
       return 1;
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;

src/gallium/drivers/r600/r600_state_common.c

@@ -2199,10 +2199,13 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		if (has_user_indices && (R600_BIG_ENDIAN || indirect ||
 						 info->instance_count > 1 ||
 						 draws[0].count*index_size > 20)) {
+			unsigned start_offset = draws[0].start * index_size;
 			indexbuf = NULL;
-			u_upload_data(ctx->stream_uploader, 0,
+			u_upload_data(ctx->stream_uploader, start_offset,
                                       draws[0].count * index_size, 256,
-				      info->index.user, &index_offset, &indexbuf);
+				      (char*)info->index.user + start_offset,
+				      &index_offset, &indexbuf);
+			index_offset -= start_offset;
 			has_user_indices = false;
 		}
 		index_bias = info->index_bias;
@@ -2344,7 +2347,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 			radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
 			radeon_emit(cs, draws[0].count);
 			radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
-			radeon_emit_array(cs, info->index.user, size_dw);
+			radeon_emit_array(cs, info->index.user + draws[0].start * index_size, size_dw);
 		} else {
 			uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
 

src/gallium/drivers/radeonsi/si_get.c

@@ -157,7 +157,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_PACKED_UNIFORMS:
    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
    case PIPE_CAP_GL_SPIRV:
-   case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
    case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
    case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
    case PIPE_CAP_NO_CLIP_ON_COPY_TEX:

src/gallium/drivers/swr/swr_state.cpp

@@ -1505,10 +1505,12 @@ swr_update_derived(struct pipe_context *pipe,
              * faster than queuing many large client draws. */
             if (size >= screen->client_copy_limit) {
                post_update_dirty_flags |= SWR_BLOCK_CLIENT_DRAW;
-               p_data = (const uint8_t *) info.index.user;
+               p_data = (const uint8_t *) info.index.user +
+                        draw->start * info.index_size;
             } else {
                /* Copy indices to scratch space */
-               const void *ptr = info.index.user;
+               const void *ptr = (char*)info.index.user +
+                                 draw->start * info.index_size;
                ptr = swr_copy_to_scratch_space(
                      ctx, &ctx->scratch->index_buffer, ptr, size);
                p_data = (const uint8_t *)ptr;

src/gallium/drivers/v3d/v3dx_draw.c

@@ -1289,10 +1289,11 @@ v3d_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
                 uint32_t offset = draws[0].start * index_size;
                 struct pipe_resource *prsc;
                 if (info->has_user_indices) {
+                        unsigned start_offset = draws[0].start * info->index_size;
                         prsc = NULL;
-                        u_upload_data(v3d->uploader, 0,
+                        u_upload_data(v3d->uploader, start_offset,
                                       draws[0].count * info->index_size, 4,
-                                      info->index.user,
+                                      (char*)info->index.user + start_offset,
                                       &offset, &prsc);
                 } else {
                         prsc = info->index.resource;

src/gallium/drivers/vc4/vc4_draw.c

@@ -394,10 +394,11 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
                         index_size = 2;
                 } else {
                         if (info->has_user_indices) {
+                                unsigned start_offset = draws[0].start * info->index_size;
                                 prsc = NULL;
-                                u_upload_data(vc4->uploader, 0,
+                                u_upload_data(vc4->uploader, start_offset,
                                               draws[0].count * index_size, 4,
-                                              info->index.user,
+                                              (char*)info->index.user + start_offset,
                                               &offset, &prsc);
                         } else {
                                 prsc = info->index.resource;

src/gallium/drivers/vc4/vc4_resource.c

@@ -1084,7 +1084,7 @@ vc4_get_shadow_index_buffer(struct pipe_context *pctx,
         struct pipe_transfer *src_transfer = NULL;
         const uint32_t *src;
         if (info->has_user_indices) {
-                src = info->index.user;
+                src = (uint32_t*)((char*)info->index.user + offset);
         } else {
                 src = pipe_buffer_map_range(pctx, &orig->base,
                                             offset,

src/gallium/drivers/virgl/virgl_context.c

@@ -886,8 +886,12 @@ static void virgl_draw_vbo(struct pipe_context *ctx,
            ib.offset = draws[0].start * ib.index_size;
 
            if (ib.user_buffer) {
-                   u_upload_data(vctx->uploader, 0, draws[0].count * ib.index_size, 4,
-                                 ib.user_buffer, &ib.offset, &ib.buffer);
+                   unsigned start_offset = draws[0].start * ib.index_size;
+                   u_upload_data(vctx->uploader, start_offset,
+                                 draws[0].count * ib.index_size, 4,
+                                 (char*)ib.user_buffer + start_offset,
+                                 &ib.offset, &ib.buffer);
+                   ib.offset -= start_offset;
                    ib.user_buffer = NULL;
            }
    }

src/gallium/include/pipe/p_defines.h

@@ -962,7 +962,6 @@ enum pipe_cap
    PIPE_CAP_PACKED_STREAM_OUTPUT,
    PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED,
    PIPE_CAP_PSIZ_CLAMPED,
-   PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES,
    PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE,
    PIPE_CAP_VIEWPORT_SWIZZLE,
    PIPE_CAP_SYSTEM_SVM,

src/mesa/state_tracker/st_extensions.c

@@ -585,9 +585,7 @@ void st_init_limits(struct pipe_screen *screen,
    c->VertexBufferOffsetIsInt32 =
       screen->get_param(screen, PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET);
 
-   c->MultiDrawWithUserIndices =
-      screen->get_param(screen, PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES);
-
+   c->MultiDrawWithUserIndices = true;
    c->AllowDynamicVAOFastPath = true;
 
    c->glBeginEndBufferSize =