Commit 02fe825a authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Marge Bot
Browse files

isl, anv, iris: Add a centralized helper to select MOCS based on usage



On Gen12+, we can enable additional caches in certain usage situations.
This routes that decision making to a central place in ISL, based on
surface usage flags, and updates both drivers to use it.  (i965 doesn't
need to change because it doesn't support Gen12.)

We continue handling the "external" decision via an anv_mocs() wrapper
for now, since we store that flag in anv_bo, which isl doesn't know
about.  (We could introduce an ISL_SURF_USAGE_EXTERNAL, but I'm not
actually sure that would be cleaner.)

This patch should not have any functional nor performance effects, as
we continue selecting the exact same MOCS values for now.
Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
Part-of: <!7104>
parent 103ad427
...@@ -250,7 +250,9 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev, ...@@ -250,7 +250,9 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.buffer = res->bo, .buffer = res->bo,
.offset = res->offset, .offset = res->offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
.mocs = iris_mocs(res->bo, isl_dev), .mocs = iris_mocs(res->bo, isl_dev,
is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT),
}, },
.aux_usage = aux_usage, .aux_usage = aux_usage,
}; };
...@@ -261,7 +263,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev, ...@@ -261,7 +263,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.buffer = res->aux.bo, .buffer = res->aux.bo,
.offset = res->aux.offset, .offset = res->aux.offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
.mocs = iris_mocs(res->bo, isl_dev), .mocs = iris_mocs(res->bo, isl_dev, 0),
}; };
surf->clear_color = surf->clear_color =
iris_resource_get_clear_color(res, NULL, NULL); iris_resource_get_clear_color(res, NULL, NULL);
...@@ -269,7 +271,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev, ...@@ -269,7 +271,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.buffer = res->aux.clear_color_bo, .buffer = res->aux.clear_color_bo,
.offset = res->aux.clear_color_offset, .offset = res->aux.clear_color_offset,
.reloc_flags = 0, .reloc_flags = 0,
.mocs = iris_mocs(res->aux.clear_color_bo, isl_dev), .mocs = iris_mocs(res->aux.clear_color_bo, isl_dev, 0),
}; };
} }
} }
......
...@@ -183,7 +183,8 @@ blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch, ...@@ -183,7 +183,8 @@ blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
*addr = (struct blorp_address) { *addr = (struct blorp_address) {
.buffer = bo, .buffer = bo,
.offset = offset, .offset = offset,
.mocs = iris_mocs(bo, &batch->screen->isl_dev), .mocs = iris_mocs(bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT),
}; };
return map; return map;
......
...@@ -850,7 +850,7 @@ uint32_t iris_upload_border_color(struct iris_context *ice, ...@@ -850,7 +850,7 @@ uint32_t iris_upload_border_color(struct iris_context *ice,
void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
struct pipe_shader_buffer *buf, struct pipe_shader_buffer *buf,
struct iris_state_ref *surf_state, struct iris_state_ref *surf_state,
bool ssbo); isl_surf_usage_flags_t usage);
const struct shader_info *iris_get_shader_info(const struct iris_context *ice, const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
gl_shader_stage stage); gl_shader_stage stage);
struct iris_bo *iris_get_scratch_space(struct iris_context *ice, struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
......
...@@ -332,7 +332,8 @@ iris_update_grid_size_resource(struct iris_context *ice, ...@@ -332,7 +332,8 @@ iris_update_grid_size_resource(struct iris_context *ice,
.size_B = sizeof(grid->grid), .size_B = sizeof(grid->grid),
.format = ISL_FORMAT_RAW, .format = ISL_FORMAT_RAW,
.stride_B = 1, .stride_B = 1,
.mocs = iris_mocs(grid_bo, isl_dev)); .mocs = iris_mocs(grid_bo, isl_dev,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT));
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_CS; ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_CS;
} }
......
...@@ -153,10 +153,11 @@ void ...@@ -153,10 +153,11 @@ void
iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
struct pipe_shader_buffer *buf, struct pipe_shader_buffer *buf,
struct iris_state_ref *surf_state, struct iris_state_ref *surf_state,
bool ssbo) isl_surf_usage_flags_t usage)
{ {
struct pipe_context *ctx = &ice->ctx; struct pipe_context *ctx = &ice->ctx;
struct iris_screen *screen = (struct iris_screen *) ctx->screen; struct iris_screen *screen = (struct iris_screen *) ctx->screen;
bool ssbo = usage & ISL_SURF_USAGE_STORAGE_BIT;
void *map = void *map =
upload_state(ice->state.surface_uploader, surf_state, upload_state(ice->state.surface_uploader, surf_state,
...@@ -178,7 +179,7 @@ iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, ...@@ -178,7 +179,7 @@ iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
: ISL_FORMAT_R32G32B32A32_FLOAT, : ISL_FORMAT_R32G32B32A32_FLOAT,
.swizzle = ISL_SWIZZLE_IDENTITY, .swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = 1, .stride_B = 1,
.mocs = iris_mocs(res->bo, &screen->isl_dev)); .mocs = iris_mocs(res->bo, &screen->isl_dev, usage));
} }
static nir_ssa_def * static nir_ssa_def *
...@@ -1833,7 +1834,8 @@ iris_update_pull_constant_descriptors(struct iris_context *ice, ...@@ -1833,7 +1834,8 @@ iris_update_pull_constant_descriptors(struct iris_context *ice,
struct pipe_shader_buffer *cbuf = &shs->constbuf[i]; struct pipe_shader_buffer *cbuf = &shs->constbuf[i];
struct iris_state_ref *surf_state = &shs->constbuf_surf_state[i]; struct iris_state_ref *surf_state = &shs->constbuf_surf_state[i];
if (!surf_state->res && cbuf->buffer) { if (!surf_state->res && cbuf->buffer) {
iris_upload_ubo_ssbo_surf_state(ice, cbuf, surf_state, false); iris_upload_ubo_ssbo_surf_state(ice, cbuf, surf_state,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT);
any_new_descriptors = true; any_new_descriptors = true;
} }
} }
......
...@@ -511,6 +511,9 @@ iris_resource_configure_main(const struct iris_screen *screen, ...@@ -511,6 +511,9 @@ iris_resource_configure_main(const struct iris_screen *screen,
isl_surf_usage_flags_t usage = 0; isl_surf_usage_flags_t usage = 0;
if (templ->usage == PIPE_USAGE_STAGING)
usage |= ISL_SURF_USAGE_STAGING_BIT;
if (templ->bind & PIPE_BIND_RENDER_TARGET) if (templ->bind & PIPE_BIND_RENDER_TARGET)
usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT; usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
......
...@@ -292,9 +292,11 @@ iris_resource_bo(struct pipe_resource *p_res) ...@@ -292,9 +292,11 @@ iris_resource_bo(struct pipe_resource *p_res)
} }
static inline uint32_t static inline uint32_t
iris_mocs(const struct iris_bo *bo, const struct isl_device *dev) iris_mocs(const struct iris_bo *bo,
const struct isl_device *dev,
isl_surf_usage_flags_t usage)
{ {
return bo && bo->external ? dev->mocs.external : dev->mocs.internal; return bo && bo->external ? dev->mocs.external : isl_mocs(dev, usage);
} }
struct iris_format_info iris_format_for_usage(const struct gen_device_info *, struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
......
...@@ -697,7 +697,8 @@ init_glk_barrier_mode(struct iris_batch *batch, uint32_t value) ...@@ -697,7 +697,8 @@ init_glk_barrier_mode(struct iris_batch *batch, uint32_t value)
static void static void
init_state_base_address(struct iris_batch *batch) init_state_base_address(struct iris_batch *batch)
{ {
uint32_t mocs = batch->screen->isl_dev.mocs.internal; struct isl_device *isl_dev = &batch->screen->isl_dev;
uint32_t mocs = isl_mocs(isl_dev, 0);
flush_before_state_base_change(batch); flush_before_state_base_change(batch);
/* We program most base addresses once at context initialization time. /* We program most base addresses once at context initialization time.
...@@ -2145,7 +2146,8 @@ fill_buffer_surface_state(struct isl_device *isl_dev, ...@@ -2145,7 +2146,8 @@ fill_buffer_surface_state(struct isl_device *isl_dev,
enum isl_format format, enum isl_format format,
struct isl_swizzle swizzle, struct isl_swizzle swizzle,
unsigned offset, unsigned offset,
unsigned size) unsigned size,
isl_surf_usage_flags_t usage)
{ {
const struct isl_format_layout *fmtl = isl_format_get_layout(format); const struct isl_format_layout *fmtl = isl_format_get_layout(format);
const unsigned cpp = format == ISL_FORMAT_RAW ? 1 : fmtl->bpb / 8; const unsigned cpp = format == ISL_FORMAT_RAW ? 1 : fmtl->bpb / 8;
...@@ -2176,7 +2178,7 @@ fill_buffer_surface_state(struct isl_device *isl_dev, ...@@ -2176,7 +2178,7 @@ fill_buffer_surface_state(struct isl_device *isl_dev,
.format = format, .format = format,
.swizzle = swizzle, .swizzle = swizzle,
.stride_B = cpp, .stride_B = cpp,
.mocs = iris_mocs(res->bo, isl_dev)); .mocs = iris_mocs(res->bo, isl_dev, usage));
} }
#define SURFACE_STATE_ALIGNMENT 64 #define SURFACE_STATE_ALIGNMENT 64
...@@ -2335,7 +2337,7 @@ fill_surface_state(struct isl_device *isl_dev, ...@@ -2335,7 +2337,7 @@ fill_surface_state(struct isl_device *isl_dev,
struct isl_surf_fill_state_info f = { struct isl_surf_fill_state_info f = {
.surf = surf, .surf = surf,
.view = view, .view = view,
.mocs = iris_mocs(res->bo, isl_dev), .mocs = iris_mocs(res->bo, isl_dev, view->usage),
.address = res->bo->gtt_offset + res->offset + extra_main_offset, .address = res->bo->gtt_offset + res->offset + extra_main_offset,
.x_offset_sa = tile_x_sa, .x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa, .y_offset_sa = tile_y_sa,
...@@ -2451,7 +2453,8 @@ iris_create_sampler_view(struct pipe_context *ctx, ...@@ -2451,7 +2453,8 @@ iris_create_sampler_view(struct pipe_context *ctx,
} else { } else {
fill_buffer_surface_state(&screen->isl_dev, isv->res, map, fill_buffer_surface_state(&screen->isl_dev, isv->res, map,
isv->view.format, isv->view.swizzle, isv->view.format, isv->view.swizzle,
tmpl->u.buf.offset, tmpl->u.buf.size); tmpl->u.buf.offset, tmpl->u.buf.size,
ISL_SURF_USAGE_TEXTURE_BIT);
} }
upload_surface_states(ice->state.surface_uploader, &isv->surface_state); upload_surface_states(ice->state.surface_uploader, &isv->surface_state);
...@@ -2677,7 +2680,8 @@ iris_create_surface(struct pipe_context *ctx, ...@@ -2677,7 +2680,8 @@ iris_create_surface(struct pipe_context *ctx,
struct isl_surf_fill_state_info f = { struct isl_surf_fill_state_info f = {
.surf = &isl_surf, .surf = &isl_surf,
.view = view, .view = view,
.mocs = iris_mocs(res->bo, &screen->isl_dev), .mocs = iris_mocs(res->bo, &screen->isl_dev,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
.address = res->bo->gtt_offset + offset_B, .address = res->bo->gtt_offset + offset_B,
.x_offset_sa = tile_x_sa, .x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa, .y_offset_sa = tile_y_sa,
...@@ -2780,7 +2784,8 @@ iris_set_shader_images(struct pipe_context *ctx, ...@@ -2780,7 +2784,8 @@ iris_set_shader_images(struct pipe_context *ctx,
if (isl_fmt == ISL_FORMAT_RAW) { if (isl_fmt == ISL_FORMAT_RAW) {
fill_buffer_surface_state(&screen->isl_dev, res, map, fill_buffer_surface_state(&screen->isl_dev, res, map,
isl_fmt, ISL_SWIZZLE_IDENTITY, isl_fmt, ISL_SWIZZLE_IDENTITY,
0, res->bo->size); 0, res->bo->size,
ISL_SURF_USAGE_STORAGE_BIT);
} else { } else {
unsigned aux_modes = aux_usages; unsigned aux_modes = aux_usages;
while (aux_modes) { while (aux_modes) {
...@@ -2802,7 +2807,8 @@ iris_set_shader_images(struct pipe_context *ctx, ...@@ -2802,7 +2807,8 @@ iris_set_shader_images(struct pipe_context *ctx,
fill_buffer_surface_state(&screen->isl_dev, res, map, fill_buffer_surface_state(&screen->isl_dev, res, map,
isl_fmt, ISL_SWIZZLE_IDENTITY, isl_fmt, ISL_SWIZZLE_IDENTITY,
img->u.buf.offset, img->u.buf.size); img->u.buf.offset, img->u.buf.size,
ISL_SURF_USAGE_STORAGE_BIT);
fill_buffer_image_param(&image_params[start_slot + i], fill_buffer_image_param(&image_params[start_slot + i],
img->format, img->u.buf.size); img->format, img->u.buf.size);
} }
...@@ -3132,7 +3138,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, ...@@ -3132,7 +3138,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
info.depth_surf = &zres->surf; info.depth_surf = &zres->surf;
info.depth_address = zres->bo->gtt_offset + zres->offset; info.depth_address = zres->bo->gtt_offset + zres->offset;
info.mocs = iris_mocs(zres->bo, isl_dev); info.mocs = iris_mocs(zres->bo, isl_dev, view.usage);
view.format = zres->surf.format; view.format = zres->surf.format;
...@@ -3150,7 +3156,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, ...@@ -3150,7 +3156,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset; info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset;
if (!zres) { if (!zres) {
view.format = stencil_res->surf.format; view.format = stencil_res->surf.format;
info.mocs = iris_mocs(stencil_res->bo, isl_dev); info.mocs = iris_mocs(stencil_res->bo, isl_dev, view.usage);
} }
} }
} }
...@@ -3325,7 +3331,8 @@ upload_sysvals(struct iris_context *ice, ...@@ -3325,7 +3331,8 @@ upload_sysvals(struct iris_context *ice,
cbuf->buffer_size = upload_size; cbuf->buffer_size = upload_size;
iris_upload_ubo_ssbo_surf_state(ice, cbuf, iris_upload_ubo_ssbo_surf_state(ice, cbuf,
&shs->constbuf_surf_state[sysval_cbuf_index], false); &shs->constbuf_surf_state[sysval_cbuf_index],
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT);
shs->sysvals_need_upload = false; shs->sysvals_need_upload = false;
} }
...@@ -3366,7 +3373,9 @@ iris_set_shader_buffers(struct pipe_context *ctx, ...@@ -3366,7 +3373,9 @@ iris_set_shader_buffers(struct pipe_context *ctx,
shs->bound_ssbos |= 1 << (start_slot + i); shs->bound_ssbos |= 1 << (start_slot + i);
iris_upload_ubo_ssbo_surf_state(ice, ssbo, surf_state, true); isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
iris_upload_ubo_ssbo_surf_state(ice, ssbo, surf_state, usage);
res->bind_history |= PIPE_BIND_SHADER_BUFFER; res->bind_history |= PIPE_BIND_SHADER_BUFFER;
res->bind_stages |= 1 << stage; res->bind_stages |= 1 << stage;
...@@ -3436,7 +3445,8 @@ iris_set_vertex_buffers(struct pipe_context *ctx, ...@@ -3436,7 +3445,8 @@ iris_set_vertex_buffers(struct pipe_context *ctx,
vb.BufferSize = res->base.width0 - (int) buffer->buffer_offset; vb.BufferSize = res->base.width0 - (int) buffer->buffer_offset;
vb.BufferStartingAddress = vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset); ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
vb.MOCS = iris_mocs(res->bo, &screen->isl_dev); vb.MOCS = iris_mocs(res->bo, &screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT);
} else { } else {
vb.NullVertexBuffer = true; vb.NullVertexBuffer = true;
} }
...@@ -3739,7 +3749,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx, ...@@ -3739,7 +3749,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
sob.SOBufferEnable = true; sob.SOBufferEnable = true;
sob.StreamOffsetWriteEnable = true; sob.StreamOffsetWriteEnable = true;
sob.StreamOutputBufferOffsetAddressEnable = true; sob.StreamOutputBufferOffsetAddressEnable = true;
sob.MOCS = iris_mocs(res->bo, &screen->isl_dev); sob.MOCS = iris_mocs(res->bo, &screen->isl_dev, 0);
sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1; sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
sob.StreamOffset = offset; sob.StreamOffset = offset;
...@@ -5183,7 +5193,8 @@ iris_update_surface_base_address(struct iris_batch *batch, ...@@ -5183,7 +5193,8 @@ iris_update_surface_base_address(struct iris_batch *batch,
if (batch->last_surface_base_address == binder->bo->gtt_offset) if (batch->last_surface_base_address == binder->bo->gtt_offset)
return; return;
uint32_t mocs = batch->screen->isl_dev.mocs.internal; struct isl_device *isl_dev = &batch->screen->isl_dev;
uint32_t mocs = isl_mocs(isl_dev, 0);
iris_batch_sync_region_start(batch); iris_batch_sync_region_start(batch);
...@@ -5364,7 +5375,7 @@ emit_push_constant_packets(struct iris_context *ice, ...@@ -5364,7 +5375,7 @@ emit_push_constant_packets(struct iris_context *ice,
iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) { iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
pkt._3DCommandSubOpcode = push_constant_opcodes[stage]; pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
#if GEN_GEN >= 12 #if GEN_GEN >= 12
pkt.MOCS = isl_dev->mocs.internal; pkt.MOCS = isl_mocs(isl_dev, 0);
#endif #endif
if (prog_data) { if (prog_data) {
/* The Skylake PRM contains the following restriction: /* The Skylake PRM contains the following restriction:
...@@ -5415,7 +5426,7 @@ emit_push_constant_packet_all(struct iris_context *ice, ...@@ -5415,7 +5426,7 @@ emit_push_constant_packet_all(struct iris_context *ice,
assert(n <= max_pointers); assert(n <= max_pointers);
iris_pack_command(GENX(3DSTATE_CONSTANT_ALL), dw, all) { iris_pack_command(GENX(3DSTATE_CONSTANT_ALL), dw, all) {
all.DWordLength = num_dwords - 2; all.DWordLength = num_dwords - 2;
all.MOCS = isl_dev->mocs.internal; all.MOCS = isl_mocs(isl_dev, 0);
all.ShaderUpdateEnable = shader_mask; all.ShaderUpdateEnable = shader_mask;
all.PointerBufferMask = (1 << n) - 1; all.PointerBufferMask = (1 << n) - 1;
} }
...@@ -6159,7 +6170,8 @@ iris_upload_dirty_render_state(struct iris_context *ice, ...@@ -6159,7 +6170,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
vb.BufferStartingAddress = vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.draw_params.offset); (int) ice->draw.draw_params.offset);
vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev); vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT);
} }
dynamic_bound |= 1ull << count; dynamic_bound |= 1ull << count;
count++; count++;
...@@ -6181,7 +6193,8 @@ iris_upload_dirty_render_state(struct iris_context *ice, ...@@ -6181,7 +6193,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
vb.BufferStartingAddress = vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.derived_draw_params.offset); (int) ice->draw.derived_draw_params.offset);
vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev); vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT);
} }
dynamic_bound |= 1ull << count; dynamic_bound |= 1ull << count;
count++; count++;
...@@ -6440,7 +6453,8 @@ iris_upload_render_state(struct iris_context *ice, ...@@ -6440,7 +6453,8 @@ iris_upload_render_state(struct iris_context *ice,
uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)]; uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)];
iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) { iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) {
ib.IndexFormat = draw->index_size >> 1; ib.IndexFormat = draw->index_size >> 1;
ib.MOCS = iris_mocs(bo, &batch->screen->isl_dev); ib.MOCS = iris_mocs(bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_INDEX_BUFFER_BIT);
ib.BufferSize = bo->size - offset; ib.BufferSize = bo->size - offset;
ib.BufferStartingAddress = ro_bo(NULL, bo->gtt_offset + offset); ib.BufferStartingAddress = ro_bo(NULL, bo->gtt_offset + offset);
} }
......
...@@ -154,6 +154,15 @@ isl_device_setup_mocs(struct isl_device *dev) ...@@ -154,6 +154,15 @@ isl_device_setup_mocs(struct isl_device *dev)
} }
} }
/**
* Return an appropriate MOCS entry for the given usage flags.
*/
uint32_t
isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage)
{
return dev->mocs.internal;
}
void void
isl_device_init(struct isl_device *dev, isl_device_init(struct isl_device *dev,
const struct gen_device_info *info, const struct gen_device_info *info,
......
...@@ -917,6 +917,10 @@ typedef uint64_t isl_surf_usage_flags_t; ...@@ -917,6 +917,10 @@ typedef uint64_t isl_surf_usage_flags_t;
#define ISL_SURF_USAGE_HIZ_BIT (1u << 13) #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
#define ISL_SURF_USAGE_MCS_BIT (1u << 14) #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
#define ISL_SURF_USAGE_CCS_BIT (1u << 15) #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
#define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 16)
#define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 17)
#define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 18)
#define ISL_SURF_USAGE_STAGING_BIT (1u << 19)
/** @} */ /** @} */
/** /**
...@@ -1996,6 +2000,8 @@ isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second); ...@@ -1996,6 +2000,8 @@ isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
struct isl_swizzle struct isl_swizzle
isl_swizzle_invert(struct isl_swizzle swizzle); isl_swizzle_invert(struct isl_swizzle swizzle);
uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage);
#define isl_surf_init(dev, surf, ...) \ #define isl_surf_init(dev, surf, ...) \
isl_surf_init_s((dev), (surf), \ isl_surf_init_s((dev), (surf), \
&(struct isl_surf_init_info) { __VA_ARGS__ }); &(struct isl_surf_init_info) { __VA_ARGS__ });
......
...@@ -158,7 +158,9 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device, ...@@ -158,7 +158,9 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
.addr = { .addr = {
.buffer = buffer->address.bo, .buffer = buffer->address.bo,
.offset = buffer->address.offset + offset, .offset = buffer->address.offset + offset,
.mocs = anv_mocs_for_bo(device, buffer->address.bo), .mocs = anv_mocs(device, buffer->address.bo,
is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT),
}, },
}; };
...@@ -209,13 +211,17 @@ get_blorp_surf_for_anv_image(const struct anv_device *device, ...@@ -209,13 +211,17 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
aspect, usage, layout); aspect, usage, layout);
} }
isl_surf_usage_flags_t mocs_usage =
(usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) ?
ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
const struct anv_surface *surface = &image->planes[plane].surface; const struct anv_surface *surface = &image->planes[plane].surface;
*blorp_surf = (struct blorp_surf) { *blorp_surf = (struct blorp_surf) {
.surf = &surface->isl, .surf = &surface->isl,
.addr = { .addr = {
.buffer = image->planes[plane].address.bo, .buffer = image->planes[plane].address.bo,
.offset = image->planes[plane].address.offset + surface->offset, .offset = image->planes[plane].address.offset + surface->offset,
.mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo), .mocs = anv_mocs(device, image->planes[plane].address.bo, mocs_usage),
}, },
}; };
...@@ -225,7 +231,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device, ...@@ -225,7 +231,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
blorp_surf->aux_addr = (struct blorp_address) { blorp_surf->aux_addr = (struct blorp_address) {
.buffer = image->planes[plane].address.bo, .buffer = image->planes[plane].address.bo,
.offset = image->planes[plane].address.offset + aux_surface->offset, .offset = image->planes[plane].address.offset + aux_surface->offset,
.mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo), .mocs = anv_mocs(device, image->planes[plane].address.bo, 0),
}; };
blorp_surf->aux_usage = aux_usage; blorp_surf->aux_usage = aux_usage;
...@@ -277,7 +283,8 @@ get_blorp_surf_for_anv_shadow_image(const struct anv_device *device, ...@@ -277,7 +283,8 @@ get_blorp_surf_for_anv_shadow_image(const struct anv_device *device,
.buffer = image->planes[plane].address.bo, .buffer = image->planes[plane].address.bo,
.offset = image->planes[plane].address.offset + .offset = image->planes[plane].address.offset +
image->planes[plane].shadow_surface.offset, image->planes[plane].shadow_surface.offset,
.mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo), .mocs = anv_mocs(device, image->planes[plane].address.bo,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
}, },
}; };
...@@ -948,12 +955,14 @@ copy_buffer(struct anv_device *device, ...@@ -948,12 +955,14 @@ copy_buffer(struct anv_device *device,
struct blorp_address src = { struct blorp_address src = {
.buffer = src_buffer->address.bo, .buffer = src_buffer->address.bo,
.offset = src_buffer->address.offset + region->srcOffset, .offset = src_buffer->address.offset + region->srcOffset,
.mocs = anv_mocs_for_bo(device