iris_resource.c 70.7 KB
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/*
 * Copyright © 2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
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 */
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/**
 * @file iris_resource.c
 *
 * Resources are images, buffers, and other objects used by the GPU.
 *
 * XXX: explain resources
 */

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#include <stdio.h>
#include <errno.h>
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "pipe/p_screen.h"
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#include "util/os_memory.h"
#include "util/u_cpu_detect.h"
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#include "util/u_inlines.h"
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#include "util/format/u_format.h"
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#include "util/u_threaded_context.h"
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#include "util/u_transfer.h"
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#include "util/u_transfer_helper.h"
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#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
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#include "iris_batch.h"
#include "iris_context.h"
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#include "iris_resource.h"
#include "iris_screen.h"
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#include "intel/common/gen_aux_map.h"
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#include "intel/dev/gen_debug.h"
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#include "isl/isl.h"
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#include "drm-uapi/drm_fourcc.h"
#include "drm-uapi/i915_drm.h"

enum modifier_priority {
   MODIFIER_PRIORITY_INVALID = 0,
   MODIFIER_PRIORITY_LINEAR,
   MODIFIER_PRIORITY_X,
   MODIFIER_PRIORITY_Y,
   MODIFIER_PRIORITY_Y_CCS,
};

static const uint64_t priority_to_modifier[] = {
   [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
   [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
   [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
   [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
   [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
};

static bool
modifier_is_supported(const struct gen_device_info *devinfo,
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                      enum pipe_format pfmt, uint64_t modifier)
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{
   /* XXX: do something real */
   switch (modifier) {
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   case I915_FORMAT_MOD_Y_TILED_CCS: {
      if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
         return false;

      enum isl_format rt_format =
         iris_format_for_usage(devinfo, pfmt,
                               ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt;

      enum isl_format linear_format = isl_format_srgb_to_linear(rt_format);

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      if (linear_format == ISL_FORMAT_UNSUPPORTED ||
          !isl_format_supports_ccs_e(devinfo, linear_format))
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         return false;

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      return devinfo->gen >= 9 && devinfo->gen <= 11;
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   }
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   case I915_FORMAT_MOD_Y_TILED:
   case I915_FORMAT_MOD_X_TILED:
   case DRM_FORMAT_MOD_LINEAR:
      return true;
   case DRM_FORMAT_MOD_INVALID:
   default:
      return false;
   }
}

static uint64_t
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select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
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                     const uint64_t *modifiers,
                     int count)
{
   enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;

   for (int i = 0; i < count; i++) {
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      if (!modifier_is_supported(devinfo, pfmt, modifiers[i]))
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         continue;

      switch (modifiers[i]) {
      case I915_FORMAT_MOD_Y_TILED_CCS:
         prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
         break;
      case I915_FORMAT_MOD_Y_TILED:
         prio = MAX2(prio, MODIFIER_PRIORITY_Y);
         break;
      case I915_FORMAT_MOD_X_TILED:
         prio = MAX2(prio, MODIFIER_PRIORITY_X);
         break;
      case DRM_FORMAT_MOD_LINEAR:
         prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
         break;
      case DRM_FORMAT_MOD_INVALID:
      default:
         break;
      }
   }

   return priority_to_modifier[prio];
}

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enum isl_surf_dim
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target_to_isl_surf_dim(enum pipe_texture_target target)
{
   switch (target) {
   case PIPE_BUFFER:
   case PIPE_TEXTURE_1D:
   case PIPE_TEXTURE_1D_ARRAY:
      return ISL_SURF_DIM_1D;
   case PIPE_TEXTURE_2D:
   case PIPE_TEXTURE_CUBE:
   case PIPE_TEXTURE_RECT:
   case PIPE_TEXTURE_2D_ARRAY:
   case PIPE_TEXTURE_CUBE_ARRAY:
      return ISL_SURF_DIM_2D;
   case PIPE_TEXTURE_3D:
      return ISL_SURF_DIM_3D;
   case PIPE_MAX_TEXTURE_TYPES:
      break;
   }
   unreachable("invalid texture type");
}

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static void
iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
                            enum pipe_format pfmt,
                            int max,
                            uint64_t *modifiers,
                            unsigned int *external_only,
                            int *count)
{
   struct iris_screen *screen = (void *) pscreen;
   const struct gen_device_info *devinfo = &screen->devinfo;

   uint64_t all_modifiers[] = {
      DRM_FORMAT_MOD_LINEAR,
      I915_FORMAT_MOD_X_TILED,
      I915_FORMAT_MOD_Y_TILED,
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      I915_FORMAT_MOD_Y_TILED_CCS,
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   };

   int supported_mods = 0;

   for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
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      if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i]))
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         continue;

      if (supported_mods < max) {
         if (modifiers)
            modifiers[supported_mods] = all_modifiers[i];

         if (external_only)
            external_only[supported_mods] = util_format_is_yuv(pfmt);
      }

      supported_mods++;
   }

   *count = supported_mods;
}

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static isl_surf_usage_flags_t
pipe_bind_to_isl_usage(unsigned bindings)
{
   isl_surf_usage_flags_t usage = 0;

   if (bindings & PIPE_BIND_RENDER_TARGET)
      usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;

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   if (bindings & PIPE_BIND_SAMPLER_VIEW)
      usage |= ISL_SURF_USAGE_TEXTURE_BIT;

   if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
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      usage |= ISL_SURF_USAGE_STORAGE_BIT;

   if (bindings & PIPE_BIND_DISPLAY_TARGET)
      usage |= ISL_SURF_USAGE_DISPLAY_BIT;

   return usage;
}

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enum isl_format
iris_image_view_get_format(struct iris_context *ice,
                           const struct pipe_image_view *img)
{
   struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
   const struct gen_device_info *devinfo = &screen->devinfo;

   isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
   enum isl_format isl_fmt =
      iris_format_for_usage(devinfo, img->format, usage).fmt;

   if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
      /* On Gen8, try to use typed surfaces reads (which support a
       * limited number of formats), and if not possible, fall back
       * to untyped reads.
       */
      if (devinfo->gen == 8 &&
          !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
         return ISL_FORMAT_RAW;
      else
         return isl_lower_storage_image_format(devinfo, isl_fmt);
   }

   return isl_fmt;
}

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struct pipe_resource *
iris_resource_get_separate_stencil(struct pipe_resource *p_res)
{
   /* For packed depth-stencil, we treat depth as the primary resource
    * and store S8 as the "second plane" resource.
    */
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   if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT)
      return p_res->next;

   return NULL;

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}

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static void
iris_resource_set_separate_stencil(struct pipe_resource *p_res,
                                   struct pipe_resource *stencil)
{
   assert(util_format_has_depth(util_format_description(p_res->format)));
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   pipe_resource_reference(&p_res->next, stencil);
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}

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void
iris_get_depth_stencil_resources(struct pipe_resource *res,
                                 struct iris_resource **out_z,
                                 struct iris_resource **out_s)
{
   if (!res) {
      *out_z = NULL;
      *out_s = NULL;
      return;
   }

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   if (res->format != PIPE_FORMAT_S8_UINT) {
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      *out_z = (void *) res;
      *out_s = (void *) iris_resource_get_separate_stencil(res);
   } else {
      *out_z = NULL;
      *out_s = (void *) res;
   }
}

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enum isl_dim_layout
iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
                        enum isl_tiling tiling,
                        enum pipe_texture_target target)
{
   switch (target) {
   case PIPE_TEXTURE_1D:
   case PIPE_TEXTURE_1D_ARRAY:
      return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
              ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);

   case PIPE_TEXTURE_2D:
   case PIPE_TEXTURE_2D_ARRAY:
   case PIPE_TEXTURE_RECT:
   case PIPE_TEXTURE_CUBE:
   case PIPE_TEXTURE_CUBE_ARRAY:
      return ISL_DIM_LAYOUT_GEN4_2D;

   case PIPE_TEXTURE_3D:
      return (devinfo->gen >= 9 ?
              ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);

   case PIPE_MAX_TEXTURE_TYPES:
   case PIPE_BUFFER:
      break;
   }
   unreachable("invalid texture type");
}

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void
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iris_resource_disable_aux(struct iris_resource *res)
{
   iris_bo_unreference(res->aux.bo);
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   iris_bo_unreference(res->aux.clear_color_bo);
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   free(res->aux.state);

   res->aux.usage = ISL_AUX_USAGE_NONE;
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   res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
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   res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
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   res->aux.has_hiz = 0;
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   res->aux.surf.size_B = 0;
   res->aux.bo = NULL;
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   res->aux.extra_aux.surf.size_B = 0;
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   res->aux.clear_color_bo = NULL;
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   res->aux.state = NULL;
}

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static void
iris_resource_destroy(struct pipe_screen *screen,
                      struct pipe_resource *resource)
{
   struct iris_resource *res = (struct iris_resource *)resource;

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   if (resource->target == PIPE_BUFFER)
      util_range_destroy(&res->valid_buffer_range);

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   iris_resource_disable_aux(res);

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   iris_bo_unreference(res->bo);
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   iris_pscreen_unref(res->base.screen);

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   free(res);
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}

static struct iris_resource *
iris_alloc_resource(struct pipe_screen *pscreen,
                    const struct pipe_resource *templ)
{
   struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
   if (!res)
      return NULL;

   res->base = *templ;
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   res->base.screen = iris_pscreen_ref(pscreen);
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   pipe_reference_init(&res->base.reference, 1);

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   res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
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   res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
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   if (templ->target == PIPE_BUFFER)
      util_range_init(&res->valid_buffer_range);

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   return res;
}

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unsigned
iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
{
   if (res->surf.dim == ISL_SURF_DIM_3D)
      return minify(res->surf.logical_level0_px.depth, level);
   else
      return res->surf.logical_level0_px.array_len;
}

static enum isl_aux_state **
create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
{
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   assert(res->aux.state == NULL);

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   uint32_t total_slices = 0;
   for (uint32_t level = 0; level < res->surf.levels; level++)
      total_slices += iris_get_num_logical_layers(res, level);

   const size_t per_level_array_size =
      res->surf.levels * sizeof(enum isl_aux_state *);

   /* We're going to allocate a single chunk of data for both the per-level
    * reference array and the arrays of aux_state.  This makes cleanup
    * significantly easier.
    */
   const size_t total_size =
      per_level_array_size + total_slices * sizeof(enum isl_aux_state);

   void *data = malloc(total_size);
   if (!data)
      return NULL;

   enum isl_aux_state **per_level_arr = data;
   enum isl_aux_state *s = data + per_level_array_size;
   for (uint32_t level = 0; level < res->surf.levels; level++) {
      per_level_arr[level] = s;
      const unsigned level_layers = iris_get_num_logical_layers(res, level);
      for (uint32_t a = 0; a < level_layers; a++)
         *(s++) = initial;
   }
   assert((void *)s == data + total_size);

   return per_level_arr;
}

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static unsigned
iris_get_aux_clear_color_state_size(struct iris_screen *screen)
{
   const struct gen_device_info *devinfo = &screen->devinfo;
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   return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
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}

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static void
map_aux_addresses(struct iris_screen *screen, struct iris_resource *res)
{
   const struct gen_device_info *devinfo = &screen->devinfo;
   if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
      void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
      assert(aux_map_ctx);
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      const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
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         res->aux.extra_aux.offset : res->aux.offset;
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      gen_aux_map_add_image(aux_map_ctx, &res->surf, res->bo->gtt_offset,
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                            res->aux.bo->gtt_offset + aux_offset);
      res->bo->aux_map_address = res->aux.bo->gtt_offset;
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   }
}

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static bool
want_ccs_e_for_format(const struct gen_device_info *devinfo,
                      enum isl_format format)
{
   if (!isl_format_supports_ccs_e(devinfo, format))
      return false;

   const struct isl_format_layout *fmtl = isl_format_get_layout(format);

   /* CCS_E seems to significantly hurt performance with 32-bit floating
    * point formats.  For example, Paraview's "Wavelet Volume" case uses
    * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
    * formats causes a 62% FPS drop.
    *
    * However, many benchmarks seem to use 16-bit float with no issues.
    */
   if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT)
      return false;

   return true;
}

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/**
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 * Configure aux for the resource, but don't allocate it. For images which
 * might be shared with modifiers, we must allocate the image and aux data in
 * a single bo.
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 *
 * Returns false on unexpected error (e.g. allocation failed, or invalid
 * configuration result).
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 */
static bool
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iris_resource_configure_aux(struct iris_screen *screen,
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                            struct iris_resource *res, bool imported,
                            uint64_t *aux_size_B,
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                            uint32_t *alloc_flags)
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{
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   const struct gen_device_info *devinfo = &screen->devinfo;

   /* Try to create the auxiliary surfaces allowed by the modifier or by
    * the user if no modifier is specified.
    */
   assert(!res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
                            res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);

   const bool has_mcs = !res->mod_info &&
      isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);

   const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) &&
      isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
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   const bool has_ccs =
      ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) ||
       (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
      isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf,
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                            &res->aux.extra_aux.surf, 0);

   /* Having both HIZ and MCS is impossible. */
   assert(!has_mcs || !has_hiz);

   /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
   if (has_ccs && (has_mcs || has_hiz)) {
      assert(res->aux.extra_aux.surf.size_B > 0 &&
             res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT);
      assert(res->aux.surf.size_B > 0 &&
             res->aux.surf.usage &
             (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT));
   }
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   if (res->mod_info && has_ccs) {
      /* Only allow a CCS modifier if the aux was created successfully. */
      res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
   } else if (has_mcs) {
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      res->aux.possible_usages |=
         1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
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   } else if (has_hiz) {
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      if (!has_ccs) {
         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
      } else if (res->surf.samples == 1 &&
                 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
         /* If this resource is single-sampled and will be used as a texture,
          * put the HiZ surface in write-through mode so that we can sample
          * from it.
          */
         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
      } else {
         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
      }
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   } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) {
      res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
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   } else if (has_ccs) {
      if (want_ccs_e_for_format(devinfo, res->surf.format))
         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;

      if (isl_format_supports_ccs_d(devinfo, res->surf.format))
         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
   }

   res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;

   res->aux.sampler_usages = res->aux.possible_usages;

   /* We don't always support sampling with hiz. But when we do, it must be
    * single sampled.
    */
   if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
      res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);

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   /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
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   res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);

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   enum isl_aux_state initial_state;
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   *aux_size_B = 0;
   *alloc_flags = 0;
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   assert(!res->aux.bo);

   switch (res->aux.usage) {
   case ISL_AUX_USAGE_NONE:
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      /* Having no aux buffer is only okay if there's no modifier with aux. */
      return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
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   case ISL_AUX_USAGE_HIZ:
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   case ISL_AUX_USAGE_HIZ_CCS:
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   case ISL_AUX_USAGE_HIZ_CCS_WT:
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      initial_state = ISL_AUX_STATE_AUX_INVALID;
      break;
   case ISL_AUX_USAGE_MCS:
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   case ISL_AUX_USAGE_MCS_CCS:
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      /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
       *
       *    "When MCS buffer is enabled and bound to MSRT, it is required
       *     that it is cleared prior to any rendering."
       *
       * Since we only use the MCS buffer for rendering, we just clear it
       * immediately on allocation.  The clear value for MCS buffers is all
       * 1's, so we simply memset it to 0xff.
       */
      initial_state = ISL_AUX_STATE_CLEAR;
      break;
   case ISL_AUX_USAGE_CCS_D:
   case ISL_AUX_USAGE_CCS_E:
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   case ISL_AUX_USAGE_STC_CCS:
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      /* When CCS_E is used, we need to ensure that the CCS starts off in
       * a valid state.  From the Sky Lake PRM, "MCS Buffer for Render
       * Target(s)":
       *
       *    "If Software wants to enable Color Compression without Fast
       *     clear, Software needs to initialize MCS with zeros."
       *
       * A CCS value of 0 indicates that the corresponding block is in the
       * pass-through state which is what we want.
       *
       * For CCS_D, do the same thing.  On Gen9+, this avoids having any
       * undefined bits in the aux buffer.
       */
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      if (imported) {
         assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
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         initial_state =
            isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
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      } else {
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         initial_state = ISL_AUX_STATE_PASS_THROUGH;
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      }
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      *alloc_flags |= BO_ALLOC_ZEROED;
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      break;
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   case ISL_AUX_USAGE_MC:
      unreachable("Unsupported aux mode");
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   }

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   /* Create the aux_state for the auxiliary buffer. */
   res->aux.state = create_aux_state_map(res, initial_state);
   if (!res->aux.state)
      return false;
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   /* Increase the aux offset if the main and aux surfaces will share a BO. */
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   res->aux.offset =
      !res->mod_info || res->mod_info->aux_usage == res->aux.usage ?
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      ALIGN(res->surf.size_B, res->aux.surf.alignment_B) : 0;
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   uint64_t size = res->aux.surf.size_B;

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   /* Allocate space in the buffer for storing the CCS. */
   if (res->aux.extra_aux.surf.size_B > 0) {
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      const uint64_t padded_aux_size =
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         ALIGN(size, res->aux.extra_aux.surf.alignment_B);
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      res->aux.extra_aux.offset = res->aux.offset + padded_aux_size;
      size = padded_aux_size + res->aux.extra_aux.surf.size_B;
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   }

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   /* Allocate space in the buffer for storing the clear color. On modern
    * platforms (gen > 9), we can read it directly from such buffer.
    *
    * On gen <= 9, we are going to store the clear color on the buffer
    * anyways, and copy it back to the surface state during state emission.
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    *
    * Also add some padding to make sure the fast clear color state buffer
    * starts at a 4K alignment. We believe that 256B might be enough, but due
    * to lack of testing we will leave this as 4K for now.
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    */
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   res->aux.clear_color_offset = res->aux.offset + size;
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   size += iris_get_aux_clear_color_state_size(screen);
   *aux_size_B = size;
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   if (isl_aux_usage_has_hiz(res->aux.usage)) {
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      for (unsigned level = 0; level < res->surf.levels; ++level) {
         uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
         uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);

         /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
          * For LOD == 0, we can grow the dimensions to make it work.
          */
         if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
            res->aux.has_hiz |= 1 << level;
      }
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   }
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   return true;
}

/**
 * Initialize the aux buffer contents.
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 *
 * Returns false on unexpected error (e.g. mapping a BO failed).
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 */
static bool
iris_resource_init_aux_buf(struct iris_resource *res, uint32_t alloc_flags,
                           unsigned clear_color_state_size)
{
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   if (!(alloc_flags & BO_ALLOC_ZEROED)) {
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      void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
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      if (!map)
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         return false;

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      if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) {
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         uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
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         memset((char*)map + res->aux.offset, memset_value,
                res->aux.surf.size_B);
      }
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      memset((char*)map + res->aux.extra_aux.offset,
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             0, res->aux.extra_aux.surf.size_B);
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      /* Zero the indirect clear color to match ::fast_clear_color. */
      memset((char *)map + res->aux.clear_color_offset, 0,
             clear_color_state_size);

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      iris_bo_unmap(res->aux.bo);
   }

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   if (clear_color_state_size > 0) {
      res->aux.clear_color_bo = res->aux.bo;
      iris_bo_reference(res->aux.clear_color_bo);
   }
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   return true;
}
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/**
 * Allocate the initial aux surface for a resource based on aux.usage
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 *
 * Returns false on unexpected error (e.g. allocation failed, or invalid
 * configuration result).
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 */
static bool
iris_resource_alloc_separate_aux(struct iris_screen *screen,
                                 struct iris_resource *res)
{
   uint32_t alloc_flags;
   uint64_t size;
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   if (!iris_resource_configure_aux(screen, res, false, &size, &alloc_flags))
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      return false;

   if (size == 0)
      return true;

   /* Allocate the auxiliary buffer.  ISL has stricter set of alignment rules
    * the drm allocator.  Therefore, one can pass the ISL dimensions in terms
    * of bytes instead of trying to recalculate based on different format
    * block sizes.
    */
   res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size, 4096,
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                                     IRIS_MEMZONE_OTHER,
                                     isl_tiling_to_i915_tiling(res->aux.surf.tiling),
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                                     res->aux.surf.row_pitch_B, alloc_flags);
   if (!res->aux.bo) {
      return false;
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   }
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   if (!iris_resource_init_aux_buf(res, alloc_flags,
                                   iris_get_aux_clear_color_state_size(screen)))
      return false;

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   map_aux_addresses(screen, res);

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   return true;
}

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void
iris_resource_finish_aux_import(struct pipe_screen *pscreen,
                                struct iris_resource *res)
{
   struct iris_screen *screen = (struct iris_screen *)pscreen;
   assert(iris_resource_unfinished_aux_import(res));
   assert(!res->mod_info->supports_clear_color);

   struct iris_resource *aux_res = (void *) res->base.next;
   assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset &&
          aux_res->aux.bo);

   assert(res->bo == aux_res->aux.bo);
   iris_bo_reference(aux_res->aux.bo);
   res->aux.bo = aux_res->aux.bo;

   res->aux.offset = aux_res->aux.offset;

   assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B));
   assert(res->aux.clear_color_bo == NULL);
   res->aux.clear_color_offset = 0;

   assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B);

   unsigned clear_color_state_size =
      iris_get_aux_clear_color_state_size(screen);

   if (clear_color_state_size > 0) {
      res->aux.clear_color_bo =
         iris_bo_alloc(screen->bufmgr, "clear color buffer",
                       clear_color_state_size, IRIS_MEMZONE_OTHER);
      res->aux.clear_color_offset = 0;
   }

   iris_resource_destroy(&screen->base, res->base.next);
   res->base.next = NULL;
}

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static struct pipe_resource *
iris_resource_create_for_buffer(struct pipe_screen *pscreen,
                                const struct pipe_resource *templ)
{
   struct iris_screen *screen = (struct iris_screen *)pscreen;
   struct iris_resource *res = iris_alloc_resource(pscreen, templ);

   assert(templ->target == PIPE_BUFFER);
   assert(templ->height0 <= 1);
   assert(templ->depth0 <= 1);
   assert(templ->format == PIPE_FORMAT_NONE ||
          util_format_get_blocksize(templ->format) == 1);

   res->internal_format = templ->format;
   res->surf.tiling = ISL_TILING_LINEAR;

   enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
   const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
   if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
      memzone = IRIS_MEMZONE_SHADER;
      name = "shader kernels";
   } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
      memzone = IRIS_MEMZONE_SURFACE;
      name = "surface state";
   } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
      memzone = IRIS_MEMZONE_DYNAMIC;
      name = "dynamic state";
   }

   res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
   if (!res->bo) {
      iris_resource_destroy(pscreen, &res->base);
      return NULL;
   }

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   if (templ->bind & PIPE_BIND_SHARED)
      iris_bo_make_external(res->bo);

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   return &res->base;
}

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static struct pipe_resource *
iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
                                    const struct pipe_resource *templ,
                                    const uint64_t *modifiers,
                                    int modifiers_count)
{
   struct iris_screen *screen = (struct iris_screen *)pscreen;
   struct gen_device_info *devinfo = &screen->devinfo;
   struct iris_resource *res = iris_alloc_resource(pscreen, templ);
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   if (!res)
      return NULL;

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   const struct util_format_description *format_desc =
      util_format_description(templ->format);
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   const bool has_depth = util_format_has_depth(format_desc);
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   uint64_t modifier =
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      select_best_modifier(devinfo, templ->format, modifiers, modifiers_count);
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   isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
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   if (modifier != DRM_FORMAT_MOD_INVALID) {
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      res->mod_info = isl_drm_modifier_get_info(modifier);
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      tiling_flags = 1 << res->mod_info->tiling;
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   } else {
      if (modifiers_count > 0) {
         fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
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         goto fail;
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      }

      /* Use linear for staging buffers */
      if (templ->usage == PIPE_USAGE_STAGING ||
          templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
         tiling_flags = ISL_TILING_LINEAR_BIT;
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      else if (templ->bind & PIPE_BIND_SCANOUT)
         tiling_flags = ISL_TILING_X_BIT;
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   }
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   isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);

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   if (templ->target == PIPE_TEXTURE_CUBE ||
       templ->target == PIPE_TEXTURE_CUBE_ARRAY)
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      usage |= ISL_SURF_USAGE_CUBE_BIT;

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   if (templ->usage != PIPE_USAGE_STAGING) {
      if (templ->format == PIPE_FORMAT_S8_UINT)
         usage |= ISL_SURF_USAGE_STENCIL_BIT;
      else if (has_depth)
         usage |= ISL_SURF_USAGE_DEPTH_BIT;
   }
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   enum pipe_format pfmt = templ->format;
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   res->internal_format = pfmt;
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   /* Should be handled by u_transfer_helper */
   assert(!util_format_is_depth_and_stencil(pfmt));
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   struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
   assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
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   UNUSED const bool isl_surf_created_successfully =
      isl_surf_init(&screen->isl_dev, &res->surf,
                    .dim = target_to_isl_surf_dim(templ->target),
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                    .format = fmt.fmt,
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                    .width = templ->width0,
                    .height = templ->height0,
                    .depth = templ->depth0,
                    .levels = templ->last_level + 1,
                    .array_len = templ->array_size,
                    .samples = MAX2(templ->nr_samples, 1),
                    .min_alignment_B = 0,
                    .row_pitch_B = 0,
                    .usage = usage,
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                    .tiling_flags = tiling_flags);
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   assert(isl_surf_created_successfully);
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   const char *name = "miptree";
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   enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
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   unsigned int flags = 0;
   if (templ->usage == PIPE_USAGE_STAGING)
      flags |= BO_ALLOC_COHERENT;

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   /* These are for u_upload_mgr buffers only */
   assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
                            IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
                            IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
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   uint32_t aux_preferred_alloc_flags;
   uint64_t aux_size = 0;
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   if (!iris_resource_configure_aux(screen, res, false, &aux_size,
                                    &aux_preferred_alloc_flags)) {
      goto fail;
   }

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   /* Modifiers require the aux data to be in the same buffer as the main
    * surface, but we combine them even when a modifiers is not being used.
    */
   const uint64_t bo_size =
      MAX2(res->surf.size_B, res->aux.offset + aux_size);
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   uint32_t alignment = MAX2(4096, res->surf.alignment_B);
   res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment,
                                 memzone,
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                                 isl_tiling_to_i915_tiling(res->surf.tiling),
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                                 res->surf.row_pitch_B, flags);
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   if (!res->bo)
      goto fail;

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   if (aux_size > 0) {
      res->aux.bo = res->bo;
      iris_bo_reference(res->aux.bo);
      unsigned clear_color_state_size =
         iris_get_aux_clear_color_state_size(screen);
      if (!iris_resource_init_aux_buf(res, flags, clear_color_state_size))
         goto fail;
      map_aux_addresses(screen, res);
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   }

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   if (templ->bind & PIPE_BIND_SHARED)
      iris_bo_make_external(res->bo);

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   return &res->base;
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fail:
   fprintf(stderr, "XXX: resource creation failed\n");
   iris_resource_destroy(pscreen, &res->base);
   return NULL;

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}

static struct pipe_resource *
iris_resource_create(struct pipe_screen *pscreen,
                     const struct pipe_resource *templ)
{
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   if (templ->target == PIPE_BUFFER)
      return iris_resource_create_for_buffer(pscreen, templ);
   else
      return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
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}

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static uint64_t
tiling_to_modifier(uint32_t tiling)
{
   static const uint64_t map[] = {
      [I915_TILING_NONE]   = DRM_FORMAT_MOD_LINEAR,
      [I915_TILING_X]      = I915_FORMAT_MOD_X_TILED,
      [I915_TILING_Y]      = I915_FORMAT_MOD_Y_TILED,
   };

   assert(tiling < ARRAY_SIZE(map));

   return map[tiling];
}

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static struct pipe_resource *
iris_resource_from_user_memory(struct pipe_screen *pscreen,
                               const struct pipe_resource *templ,
                               void *user_memory)
{
   struct iris_screen *screen = (struct iris_screen *)pscreen;
   struct iris_bufmgr *bufmgr = screen->bufmgr;
   struct iris_resource *res = iris_alloc_resource(pscreen, templ);
   if (!res)
      return NULL;

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   assert(templ->target == PIPE_BUFFER);

   res->internal_format = templ->format;
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   res->bo = iris_bo_create_userptr(bufmgr, "user",
                                    user_memory, templ->width0,
                                    IRIS_MEMZONE_OTHER);
   if (!res->bo) {
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      iris_resource_destroy(pscreen, &res->base);
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      return NULL;
   }

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   util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
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   return &res->base;
}

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static struct pipe_resource *
iris_resource_from_handle(struct pipe_screen *pscreen,
                          const struct pipe_resource *templ,
                          struct winsys_handle *whandle,
                          unsigned usage)
{
   struct iris_screen *screen = (struct iris_screen *)pscreen;
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   struct gen_device_info *devinfo = &screen->devinfo;
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   struct iris_bufmgr *bufmgr = screen->bufmgr;
   struct iris_resource *res = iris_alloc_resource(pscreen, templ);
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   const struct isl_drm_modifier_info *mod_inf =
	   isl_drm_modifier_get_info(whandle->modifier);
   uint32_t tiling;

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   if (!res)
      return NULL;

   switch (whandle->type) {
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   case WINSYS_HANDLE_TYPE_FD:
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      if (mod_inf)
         tiling = isl_tiling_to_i915_tiling(mod_inf->tiling);
      else
         tiling = I915_TILING_LAST + 1;
      res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
                                      tiling, whandle->stride);
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      break;
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   case WINSYS_HANDLE_TYPE_SHARED:
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      res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
                                             whandle->handle);
      break;
   default:
      unreachable("invalid winsys handle type");
   }
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   if (!res->bo)
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      goto fail;
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   res->offset = whandle->offset;

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   if (mod_inf == NULL) {
      mod_inf =
         isl_drm_modifier_get_info(tiling_to_modifier(res->bo->tiling_mode));
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   }
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   assert(mod_inf);

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   res->external_format = whandle->format;
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   res->mod_info = mod_inf;
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   isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
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   const struct iris_format_info fmt =
      iris_format_for_usage(devinfo, templ->format, isl_usage);
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   res->internal_format = templ->format;
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   if (templ->target == PIPE_BUFFER) {
      res->surf.tiling = ISL_TILING_LINEAR;
   } else {
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      /* Create a surface for each plane specified by the external format. */
      if (whandle->plane < util_format_get_num_planes(whandle->format)) {
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         UNUSED const bool isl_surf_created_successfully =
            isl_surf_init(&screen->isl_dev, &res->surf,
                          .dim = target_to_isl_surf_dim(templ->target),
                          .format = fmt.fmt,
                          .width = templ->width0,
                          .height = templ->height0,
                          .depth = templ->depth0,
                          .levels = templ->last_level + 1,
                          .array_len = templ->array_size,
                          .samples = MAX2(templ->nr_samples, 1),
                          .min_alignment_B = 0,
                          .row_pitch_B = whandle->stride,
                          .usage = isl_usage,
                          .tiling_flags = 1 << res->mod_info->tiling);
         assert(isl_surf_created_successfully);
         assert(res->bo->tiling_mode ==
                isl_tiling_to_i915_tiling(res->surf.tiling));

         // XXX: create_ccs_buf_for_image?
         if (whandle->modifier == DRM_FORMAT_MOD_INVALID) {
            if (!iris_resource_alloc_separate_aux(screen, res))
               goto fail;
         } else {
            if (res->mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
               uint32_t alloc_flags;
               uint64_t size;
               bool ok = iris_resource_configure_aux(screen, res, true, &size,
                                                     &alloc_flags);
               assert(ok);
               /* The gallium dri layer will create a separate plane resource
                * for the aux image. iris_resource_finish_aux_import will
                * merge the separate aux parameters back into a single
                * iris_resource.
                */
            }
         }
      } else {
         /* Save modifier import information to reconstruct later. After
          * import, this will be available under a second image accessible
          * from the main image with res->base.next. See
          * iris_resource_finish_aux_import.
          */
         res->aux.surf.row_pitch_B = whandle->stride;
         res->aux.offset = whandle->offset;
         res->aux.bo = res->bo;
         res->bo = NULL;
      }
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   }
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   return &res->base;

fail:
   iris_resource_destroy(pscreen, &res->base);
   return NULL;
}

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static void
iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
{
   struct iris_context *ice = (struct iris_context *)ctx;
   struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
   struct iris_resource *res = (void *) resource;
   const struct isl_drm_modifier_info *mod = res->mod_info;

   iris_resource_prepare_access(ice, render_batch, res,
                                0, INTEL_REMAINING_LEVELS,
                                0, INTEL_REMAINING_LAYERS,
                                mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
                                mod ? mod->supports_clear_color : false);
}

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static void
iris_resource_disable_aux_on_first_query(struct pipe_resource *resource,
                                         unsigned usage)
{
   struct iris_resource *res = (struct iris_resource *)resource;
   bool mod_with_aux =
      res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;

   /* Disable aux usage if explicit flush not set and this is the first time
    * we are dealing with this resource and the resource was not created with
    * a modifier with aux.
    */
   if (!mod_with_aux &&
      (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
       p_atomic_read(&resource->reference.count) == 1) {
         iris_resource_disable_aux(res);
   }
}

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static bool
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iris_resource_get_param(struct pipe_screen *pscreen,
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                        struct pipe_context *context,
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                        struct pipe_resource *resource,
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                        unsigned plane,
                        unsigned layer,
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                        enum pipe_resource_param param,
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                        unsigned handle_usage,
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                        uint64_t *value)
{
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   struct iris_screen *screen = (struct iris_screen *)pscreen;
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   struct iris_resource *res = (struct iris_resource *)resource;
   bool mod_with_aux =
      res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
   bool wants_aux = mod_with_aux && plane > 0;
   bool result;
   unsigned handle;

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   if (iris_resource_unfinished_aux_import(res))
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      iris_resource_finish_aux_import(pscreen, res);
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   struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo;

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   iris_resource_disable_aux_on_first_query(resource, handle_usage);

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   switch (param) {
   case PIPE_RESOURCE_PARAM_NPLANES:
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      if (mod_with_aux) {
         *value = 2;
      } else {
         unsigned count = 0;
         for (struct pipe_resource *cur = resource; cur; cur = cur->next)
            count++;
         *value = count;
      }
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      return true;
   case PIPE_RESOURCE_PARAM_STRIDE:
      *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
      return true;
   case PIPE_RESOURCE_PARAM_OFFSET:
      *value = wants_aux ? res->aux.offset : 0;
      return true;
   case PIPE_RESOURCE_PARAM_MODIFIER:
      *value = res->mod_info ? res->mod_info->modifier :
               tiling_to_modifier(res->bo->tiling_mode);
      return true;
   case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
      result = iris_bo_flink(bo, &handle) == 0;
      if (result)
         *value = handle;
      return result;
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   case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: {
      /* Because we share the same drm file across multiple iris_screen, when
       * we export a GEM handle we must make sure it is valid in the DRM file
       * descriptor the caller is using (this is the FD given at screen
       * creation).
       */
      uint32_t handle;
      if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
         return false;
      *value = handle;
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      return true;
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   }

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   case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
      result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0;
      if (result)
         *value = handle;
      return result;
   default:
      return false;
   }
}

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static bool
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iris_resource_get_handle(struct pipe_screen *pscreen,
                         struct pipe_context *ctx,
                         struct pipe_resource *resource,
                         struct winsys_handle *whandle,
                         unsigned usage)
{
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   struct iris_screen *screen = (struct iris_screen *) pscreen;
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   struct iris_resource *res = (struct iris_resource *)resource;
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   bool mod_with_aux =
      res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
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   iris_resource_disable_aux_on_first_query(resource, usage);
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   struct iris_bo *bo;
   if (mod_with_aux && whandle->plane > 0) {
      assert(res->aux.bo);
      bo = res->aux.bo;
      whandle->stride = res->aux.surf.row_pitch_B;
      whandle->offset = res->aux.offset;
   } else {
      /* If this is a buffer, stride should be 0 - no need to special case */
      whandle->stride = res->surf.row_pitch_B;
      bo = res->bo;
   }
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   whandle->format = res->external_format;
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   whandle->modifier =
      res->mod_info ? res->mod_info->modifier
                    : tiling_to_modifier(res->bo->tiling_mode);

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#ifndef NDEBUG
   enum isl_aux_usage allowed_usage =
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      usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH ? res->aux.usage :
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      res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;

   if (res->aux.usage != allowed_usage) {
      enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
      assert(aux_state == ISL_AUX_STATE_RESOLVED ||
             aux_state == ISL_AUX_STATE_PASS_THROUGH);
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   }
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#endif
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   switch (whandle->type) {
   case WINSYS_HANDLE_TYPE_SHARED:
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      return iris_bo_flink(bo, &whandle->handle) == 0;
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   case WINSYS_HANDLE_TYPE_KMS: {
      /* Because we share the same drm file across multiple iris_screen, when
       * we export a GEM handle we must make sure it is valid in the DRM file
       * descriptor the caller is using (this is the FD given at screen
       * creation).
       */
      uint32_t handle;
      if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
         return false;
      whandle->handle = handle;
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      return true;
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   }
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   case WINSYS_HANDLE_TYPE_FD:
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      return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0;
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   }

   return false;
}

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static bool
resource_is_busy(struct iris_context *ice,
                 struct iris_resource *res)
{
   bool busy = iris_bo_busy(res->bo);

   for (int i = 0; i < IRIS_BATCH_COUNT; i++)
      busy |= iris_batch_references(&ice->batches[i], res->bo);

   return busy;
}

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static void
iris_invalidate_resource(struct pipe_context *ctx,
                         struct pipe_resource *resource)
{
   struct iris_screen *screen = (void *) ctx->screen;
   struct iris_context *ice = (void *) ctx;
   struct iris_resource *res = (void *) resource;

   if (resource->target != PIPE_BUFFER)
      return;

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   /* If it's already invalidated, don't bother doing anything. */
   if (res->valid_buffer_range.start > res->valid_buffer_range.end)
      return;

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   if (!resource_is_busy(ice, res)) {
      /* The resource is idle, so just mark that it contains no data and
       * keep using the same underlying buffer object.
       */
      util_range_set_empty(&res->valid_buffer_range);
      return;
   }

   /* Otherwise, try and replace the backing storage with a new BO. */

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   /* We can't reallocate memory we didn't allocate in the first place. */
   if (res->bo->userptr)
      return;

   // XXX: We should support this.
   if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
      return;

   struct iris_bo *old_bo = res->bo;
   struct iris_bo *new_bo =
      iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
                    iris_memzone_for_address(old_bo->gtt_offset));
   if (!new_bo)
      return;

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   /* Swap out the backing storage */
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   res->bo = new_bo;
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   /* Rebind the buffer, replacing any state referring to the old BO's
    * address, and marking state dirty so it's reemitted.
    */
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   screen->vtbl.rebind_buffer(ice, res);
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   util_range_set_empty(&res->valid_buffer_range);