si_pipe.c 13.2 KB
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/*
 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
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#include "si_pipe.h"
#include "si_public.h"

#include "radeon/radeon_uvd.h"
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#include "util/u_blitter.h"
#include "util/u_memory.h"
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#include "util/u_simple_shaders.h"
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#include "vl/vl_decoder.h"

/*
 * pipe_context
 */
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void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
	      unsigned flags)
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{
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	struct si_context *sctx = (struct si_context *)ctx;
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	struct pipe_query *render_cond = NULL;
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	boolean render_cond_cond = FALSE;
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	unsigned render_cond_mode = 0;

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	if (fence) {
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		*fence = sctx->b.ws->cs_create_fence(sctx->b.rings.gfx.cs);
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	}
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	/* Disable render condition. */
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	if (sctx->b.current_render_cond) {
		render_cond = sctx->b.current_render_cond;
		render_cond_cond = sctx->b.current_render_cond_cond;
		render_cond_mode = sctx->b.current_render_cond_mode;
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		ctx->render_condition(ctx, NULL, FALSE, 0);
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	}

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	si_context_flush(sctx, flags);
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	/* Re-enable render condition. */
	if (render_cond) {
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		ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
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	}
}

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static void si_flush_from_st(struct pipe_context *ctx,
			     struct pipe_fence_handle **fence,
			     unsigned flags)
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{
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	si_flush(ctx, fence,
		 flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
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}

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static void si_flush_from_winsys(void *ctx, unsigned flags)
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{
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	si_flush((struct pipe_context*)ctx, NULL, flags);
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}

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static void si_destroy_context(struct pipe_context *context)
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{
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	struct si_context *sctx = (struct si_context *)context;
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	si_release_all_descriptors(sctx);
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	pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
	r600_resource_reference(&sctx->border_color_table, NULL);
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	if (sctx->gs_on) {
		si_pm4_free_state(sctx, sctx->gs_on, 0);
	}
	if (sctx->gs_off) {
		si_pm4_free_state(sctx, sctx->gs_off, 0);
	}
	if (sctx->gs_rings) {
		si_pm4_free_state(sctx, sctx->gs_rings, 0);
	}

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	if (sctx->dummy_pixel_shader) {
		sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
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	}
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	for (int i = 0; i < 8; i++) {
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		sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
		sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
		sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
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	}
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	sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
	sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
	sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
	util_unreference_framebuffer_state(&sctx->framebuffer);
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	util_blitter_destroy(sctx->blitter);
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	r600_common_context_cleanup(&sctx->b);
	FREE(sctx);
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}

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static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
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{
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	struct si_context *sctx = CALLOC_STRUCT(si_context);
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	struct si_screen* sscreen = (struct si_screen *)screen;
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	int shader, i;
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	if (sctx == NULL)
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		return NULL;

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	sctx->b.b.screen = screen; /* this must be set first */
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	sctx->b.b.priv = priv;
	sctx->b.b.destroy = si_destroy_context;
	sctx->b.b.flush = si_flush_from_st;
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	sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
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	if (!r600_common_context_init(&sctx->b, &sscreen->b))
		goto fail;
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	si_init_blit_functions(sctx);
	si_init_compute_functions(sctx);
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	if (sscreen->b.info.has_uvd) {
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		sctx->b.b.create_video_codec = si_uvd_create_decoder;
		sctx->b.b.create_video_buffer = si_video_buffer_create;
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	} else {
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		sctx->b.b.create_video_codec = vl_create_decoder;
		sctx->b.b.create_video_buffer = vl_video_buffer_create;
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	}
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	sctx->b.rings.gfx.cs = sctx->b.ws->cs_create(sctx->b.ws, RING_GFX, NULL);
	sctx->b.rings.gfx.flush = si_flush_from_winsys;
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	si_init_all_descriptors(sctx);
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	/* Initialize cache_flush. */
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	sctx->cache_flush = si_atom_cache_flush;
	sctx->atoms.cache_flush = &sctx->cache_flush;
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	sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
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	switch (sctx->b.chip_class) {
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	case SI:
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	case CIK:
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		si_init_state_functions(sctx);
		si_init_config(sctx);
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		break;
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	default:
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		R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
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		goto fail;
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	}

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	sctx->b.ws->cs_set_flush_callback(sctx->b.rings.gfx.cs, si_flush_from_winsys, sctx);
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	sctx->blitter = util_blitter_create(&sctx->b.b);
	if (sctx->blitter == NULL)
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		goto fail;
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	sctx->dummy_pixel_shader =
		util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
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						     TGSI_SEMANTIC_GENERIC,
						     TGSI_INTERPOLATE_CONSTANT);
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	sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
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	/* these must be last */
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	si_begin_new_cs(sctx);
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	r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
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	/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
	 * with a NULL buffer). We need to use a dummy buffer instead. */
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	if (sctx->b.chip_class == CIK) {
		sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
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								 PIPE_USAGE_STATIC, 16);
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		sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
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		for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
			for (i = 0; i < NUM_CONST_BUFFERS; i++) {
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				sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
							      &sctx->null_const_buf);
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			}
		}

		/* Clear the NULL constant buffer, because loads should return zeros. */
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		sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
				     sctx->null_const_buf.buffer->width0, 0);
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	}

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	return &sctx->b.b;
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fail:
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	si_destroy_context(&sctx->b.b);
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	return NULL;
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}

/*
 * pipe_screen
 */

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static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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{
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	struct si_screen *sscreen = (struct si_screen *)pscreen;
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	switch (param) {
	/* Supported features (boolean caps). */
	case PIPE_CAP_TWO_SIDED_STENCIL:
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	case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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	case PIPE_CAP_ANISOTROPIC_FILTER:
	case PIPE_CAP_POINT_SPRITE:
	case PIPE_CAP_OCCLUSION_QUERY:
	case PIPE_CAP_TEXTURE_SHADOW_MAP:
	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
	case PIPE_CAP_TEXTURE_SWIZZLE:
	case PIPE_CAP_DEPTH_CLIP_DISABLE:
	case PIPE_CAP_SHADER_STENCIL_EXPORT:
	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
	case PIPE_CAP_SM3:
	case PIPE_CAP_SEAMLESS_CUBE_MAP:
	case PIPE_CAP_PRIMITIVE_RESTART:
	case PIPE_CAP_CONDITIONAL_RENDER:
	case PIPE_CAP_TEXTURE_BARRIER:
	case PIPE_CAP_INDEP_BLEND_ENABLE:
	case PIPE_CAP_INDEP_BLEND_FUNC:
	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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	case PIPE_CAP_USER_INDEX_BUFFERS:
	case PIPE_CAP_USER_CONSTANT_BUFFERS:
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	case PIPE_CAP_START_INSTANCE:
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	case PIPE_CAP_NPOT_TEXTURES:
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	case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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        case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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	case PIPE_CAP_TGSI_INSTANCEID:
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	case PIPE_CAP_COMPUTE:
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	case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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        case PIPE_CAP_TGSI_VS_LAYER:
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	case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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		return 1;
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	case PIPE_CAP_TEXTURE_MULTISAMPLE:
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		/* 2D tiling on CIK is supported since DRM 2.35.0 */
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		return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
					       sscreen->b.info.drm_minor >= 35);
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	case PIPE_CAP_TGSI_TEXCOORD:
		return 0;
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        case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
                return 64;

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	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
		return 256;

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	case PIPE_CAP_GLSL_FEATURE_LEVEL:
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		return HAVE_LLVM >= 0x0305 ? 330 : 140;
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	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
		return 1;
	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
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		return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
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	/* Unsupported features. */
	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
	case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
	case PIPE_CAP_VERTEX_COLOR_CLAMPED:
	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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	case PIPE_CAP_USER_VERTEX_BUFFERS:
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	case PIPE_CAP_CUBE_MAP_ARRAY:
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		return 0;

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	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
		return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;

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	/* Stream output. */
	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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		return sscreen->b.has_streamout ? 4 : 0;
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	case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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		return sscreen->b.has_streamout ? 1 : 0;
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	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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		return sscreen->b.has_streamout ? 32*4 : 0;
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	/* Texturing. */
	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
			return 15;
	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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		return 16384;
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	/* Render targets. */
	case PIPE_CAP_MAX_RENDER_TARGETS:
		return 8;

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	case PIPE_CAP_MAX_VIEWPORTS:
		return 1;

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	/* Timer queries, present when the clock frequency is non zero. */
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	case PIPE_CAP_QUERY_TIMESTAMP:
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	case PIPE_CAP_QUERY_TIME_ELAPSED:
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		return sscreen->b.info.r600_clock_crystal_freq != 0;
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	case PIPE_CAP_MIN_TEXEL_OFFSET:
		return -8;

	case PIPE_CAP_MAX_TEXEL_OFFSET:
		return 7;
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	case PIPE_CAP_ENDIANNESS:
		return PIPE_ENDIAN_LITTLE;
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	}
	return 0;
}

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static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
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{
	switch(shader)
	{
	case PIPE_SHADER_FRAGMENT:
	case PIPE_SHADER_VERTEX:
		break;
	case PIPE_SHADER_GEOMETRY:
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#if HAVE_LLVM < 0x0305
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		return 0;
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#endif
		break;
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	case PIPE_SHADER_COMPUTE:
		switch (param) {
		case PIPE_SHADER_CAP_PREFERRED_IR:
			return PIPE_SHADER_IR_LLVM;
		default:
			return 0;
		}
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	default:
		/* TODO: support tessellation */
		return 0;
	}

	switch (param) {
	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
		return 16384;
	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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		return 32;
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	case PIPE_SHADER_CAP_MAX_INPUTS:
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		return 32;
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	case PIPE_SHADER_CAP_MAX_TEMPS:
		return 256; /* Max native temporaries. */
	case PIPE_SHADER_CAP_MAX_ADDRS:
		/* FIXME Isn't this equal to TEMPS? */
		return 1; /* Max native address registers */
	case PIPE_SHADER_CAP_MAX_CONSTS:
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		return 4096; /* actually only memory limits this */
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	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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		return NUM_PIPE_CONST_BUFFERS;
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	case PIPE_SHADER_CAP_MAX_PREDS:
		return 0; /* FIXME */
	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
		return 1;
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	case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
		return 0;
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	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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		/* Indirection of geometry shader input dimension is not
		 * handled yet
		 */
		return shader < PIPE_SHADER_GEOMETRY;
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	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
	case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
	case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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		return 1;
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	case PIPE_SHADER_CAP_INTEGERS:
		return 1;
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	case PIPE_SHADER_CAP_SUBROUTINES:
		return 0;
	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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		return 16;
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	case PIPE_SHADER_CAP_PREFERRED_IR:
		return PIPE_SHADER_IR_TGSI;
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	}
	return 0;
}

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static void si_destroy_screen(struct pipe_screen* pscreen)
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{
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	struct si_screen *sscreen = (struct si_screen *)pscreen;
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	if (sscreen == NULL)
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		return;

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	if (!radeon_winsys_unref(sscreen->b.ws))
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		return;

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	r600_destroy_common_screen(&sscreen->b);
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}

struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
{
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	struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
	if (sscreen == NULL) {
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		return NULL;
	}

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	/* Set functions first. */
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	sscreen->b.b.context_create = si_create_context;
	sscreen->b.b.destroy = si_destroy_screen;
	sscreen->b.b.get_param = si_get_param;
	sscreen->b.b.get_shader_param = si_get_shader_param;
	sscreen->b.b.is_format_supported = si_is_format_supported;
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	sscreen->b.b.resource_create = r600_resource_create_common;
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	if (!r600_common_screen_init(&sscreen->b, ws)) {
		FREE(sscreen);
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		return NULL;
	}
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	sscreen->b.has_cp_dma = true;
	sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
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	if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
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		sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
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	/* Create the auxiliary context. This must be done last. */
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	sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
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	return &sscreen->b.b;
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}