Skip to content
Commits on Source (56)
bsd-core/*/@
bsd-core/*/machine
*~
*.1
*.3
*.5
......@@ -17,17 +14,22 @@ bsd-core/*/machine
*.o.cmd
*.sw?
*.trs
*~
.*check*
.*install*
.depend
.deps
.libs
.tmp_versions
.*check*
.*install*
/_build*
/build*
Makefile
Makefile.in
TAGS
aclocal.m4
autom4te.cache
bsd-core/*/@
bsd-core/*/machine
build-aux
bus_if.h
compile
......@@ -47,21 +49,22 @@ drm_pciids.h
export_syms
i915.kld
install-sh
libdrm/config.h.in
libdrm.pc
libdrm/config.h.in
libdrm_amdgpu.pc
libdrm_etnaviv.pc
libdrm_exynos.pc
libdrm_freedreno.pc
libdrm_intel.pc
libdrm_nouveau.pc
libdrm_radeon.pc
libdrm_omap.pc
libdrm_exynos.pc
libdrm_freedreno.pc
libdrm_amdgpu.pc
libdrm_radeon.pc
libdrm_vc4.pc
libdrm_etnaviv.pc
libkms.pc
libtool
ltmain.sh
mach64.kld
man/*.3
man/.man_fixup
mga.kld
missing
......@@ -74,35 +77,34 @@ savage.kld
sis.kld
stamp-h1
tdfx.kld
via.kld
tests/auth
tests/amdgpu/amdgpu_test
tests/auth
tests/dristat
tests/drmdevice
tests/drmsl
tests/drmstat
tests/etnaviv/etnaviv_2d_test
tests/etnaviv/etnaviv_bo_cache_test
tests/etnaviv/etnaviv_cmd_stream_test
tests/exynos/exynos_fimg2d_event
tests/exynos/exynos_fimg2d_perf
tests/exynos/exynos_fimg2d_test
tests/getclient
tests/getstats
tests/getversion
tests/hash
tests/kms/kms-steal-crtc
tests/kms/kms-universal-planes
tests/kmstest/kmstest
tests/lock
tests/openclose
tests/random
tests/setversion
tests/updatedraw
tests/modeprint/modeprint
tests/modetest/modetest
tests/name_from_fd
tests/openclose
tests/proptest/proptest
tests/kms/kms-steal-crtc
tests/kms/kms-universal-planes
tests/kmstest/kmstest
tests/vbltest/vbltest
tests/radeon/radeon_ttm
tests/exynos/exynos_fimg2d_event
tests/exynos/exynos_fimg2d_perf
tests/exynos/exynos_fimg2d_test
tests/etnaviv/etnaviv_2d_test
tests/etnaviv/etnaviv_cmd_stream_test
tests/etnaviv/etnaviv_bo_cache_test
man/*.3
tests/random
tests/setversion
tests/updatedraw
tests/vbltest/vbltest
via.kld
......@@ -55,7 +55,7 @@
latest-meson:
stage: build
image: base/archlinux:latest
image: archlinux/base:latest
before_script:
- pacman -Syu --noconfirm --needed
base-devel
......@@ -69,7 +69,7 @@ latest-meson:
latest-autotools:
stage: build
image: base/archlinux:latest
image: archlinux/base:latest
artifacts: *artifacts-autotools
before_script:
- pacman -Syu --noconfirm --needed
......
libdrm - userspace library for drm
This is libdrm, a userspace library for accessing the DRM, direct
rendering manager, on Linux, BSD and other operating systems that
support the ioctl interface. The library provides wrapper functions
for the ioctls to avoid exposing the kernel interface directly, and
for chipsets with drm memory manager, support for tracking relocations
and buffers. libdrm is a low-level library, typically used by
graphics drivers such as the Mesa DRI drivers, the X drivers, libva
and similar projects. New functionality in the kernel DRM drivers
typically requires a new libdrm, but a new libdrm will always work
with an older kernel.
----------------------------------
This is libdrm, a userspace library for accessing the DRM, direct rendering
manager, on Linux, BSD and other operating systems that support the ioctl
interface.
The library provides wrapper functions for the ioctls to avoid exposing the
kernel interface directly, and for chipsets with drm memory manager, support
for tracking relocations and buffers.
New functionality in the kernel DRM drivers typically requires a new libdrm,
but a new libdrm will always work with an older kernel.
libdrm is a low-level library, typically used by graphics drivers such as
the Mesa drivers, the X drivers, libva and similar projects.
Compiling
......
......@@ -19,6 +19,8 @@ amdgpu_bo_export
amdgpu_bo_free
amdgpu_bo_import
amdgpu_bo_inc_ref
amdgpu_bo_list_create_raw
amdgpu_bo_list_destroy_raw
amdgpu_bo_list_create
amdgpu_bo_list_destroy
amdgpu_bo_list_update
......@@ -36,6 +38,7 @@ amdgpu_cs_create_syncobj2
amdgpu_cs_ctx_create
amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
amdgpu_cs_ctx_override_priority
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
......@@ -47,6 +50,7 @@ amdgpu_query_sw_info
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
amdgpu_cs_submit_raw2
amdgpu_cs_syncobj_export_sync_file
amdgpu_cs_syncobj_import_sync_file
amdgpu_cs_syncobj_reset
......
......@@ -42,6 +42,7 @@ extern "C" {
#endif
struct drm_amdgpu_info_hw_ip;
struct drm_amdgpu_bo_list_entry;
/*--------------------------------------------------------------------------*/
/* --------------------------- Defines ------------------------------------ */
......@@ -701,7 +702,7 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
uint64_t *offset_in_bo);
/**
* Free previosuly allocated memory
* Free previously allocated memory
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param buf_handle - \c [in] Buffer handle to free
......@@ -731,7 +732,7 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
void amdgpu_bo_inc_ref(amdgpu_bo_handle bo);
/**
* Request CPU access to GPU accessable memory
* Request CPU access to GPU accessible memory
*
* \param buf_handle - \c [in] Buffer handle
* \param cpu - \c [out] CPU address to be used for access
......@@ -774,6 +775,37 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
uint64_t timeout_ns,
bool *buffer_busy);
/**
* Creates a BO list handle for command submission.
*
* \param dev - \c [in] Device handle.
* See #amdgpu_device_initialize()
* \param number_of_buffers - \c [in] Number of BOs in the list
* \param buffers - \c [in] List of BO handles
* \param result - \c [out] Created BO list handle
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2()
*/
int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
uint32_t number_of_buffers,
struct drm_amdgpu_bo_list_entry *buffers,
uint32_t *result);
/**
* Destroys a BO list handle.
*
* \param bo_list - \c [in] BO list handle.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
*/
int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list);
/**
* Creates a BO list handle for command submission.
*
......@@ -879,6 +911,21 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
*/
int amdgpu_cs_ctx_free(amdgpu_context_handle context);
/**
* Override the submission priority for the given context using a master fd.
*
* \param dev - \c [in] device handle
* \param context - \c [in] context handle for context id
* \param master_fd - \c [in] The master fd to authorize the override.
* \param priority - \c [in] The priority to assign to the context.
*
* \return 0 on success or a a negative Posix error code on failure.
*/
int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
amdgpu_context_handle context,
int master_fd,
unsigned priority);
/**
* Query reset state for the specific GPU Context
*
......@@ -1231,7 +1278,7 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
* \notes \n
* It is client responsibility to correctly handle VA assignments and usage.
* Neither kernel driver nor libdrm_amdpgu are able to prevent and
* detect wrong va assignemnt.
* detect wrong va assignment.
*
* It is client responsibility to correctly handle multi-GPU cases and to pass
* the corresponding arrays of all devices handles where corresponding VA will
......@@ -1587,6 +1634,28 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no);
/**
* Submit raw command submission to the kernel with a raw BO list handle.
*
* \param dev - \c [in] device handle
* \param context - \c [in] context handle for context id
* \param bo_list_handle - \c [in] raw bo list handle (0 for none)
* \param num_chunks - \c [in] number of CS chunks to submit
* \param chunks - \c [in] array of CS chunks
* \param seq_no - \c [out] output sequence number for submission.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw()
*/
int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
amdgpu_context_handle context,
uint32_t bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no);
void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
struct drm_amdgpu_cs_chunk_dep *dep);
void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
......
......@@ -618,6 +618,40 @@ out:
return r;
}
drm_public int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
uint32_t number_of_buffers,
struct drm_amdgpu_bo_list_entry *buffers,
uint32_t *result)
{
union drm_amdgpu_bo_list args;
int r;
memset(&args, 0, sizeof(args));
args.in.operation = AMDGPU_BO_LIST_OP_CREATE;
args.in.bo_number = number_of_buffers;
args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
args.in.bo_info_ptr = (uint64_t)(uintptr_t)buffers;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
&args, sizeof(args));
if (!r)
*result = args.out.list_handle;
return r;
}
drm_public int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev,
uint32_t bo_list)
{
union drm_amdgpu_bo_list args;
memset(&args, 0, sizeof(args));
args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
args.in.list_handle = bo_list;
return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
&args, sizeof(args));
}
drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev,
uint32_t number_of_resources,
amdgpu_bo_handle *resources,
......
......@@ -142,6 +142,31 @@ drm_public int amdgpu_cs_ctx_free(amdgpu_context_handle context)
return r;
}
drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
amdgpu_context_handle context,
int master_fd,
unsigned priority)
{
int r;
if (!dev || !context || master_fd < 0)
return -EINVAL;
union drm_amdgpu_sched args;
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE;
args.in.fd = dev->fd;
args.in.priority = priority;
args.in.ctx_id = context->id;
r = drmCommandWrite(master_fd, DRM_AMDGPU_SCHED, &args, sizeof(args));
if (r)
return r;
return 0;
}
drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
uint32_t *state, uint32_t *hangs)
{
......@@ -731,6 +756,31 @@ drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
return 0;
}
drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
amdgpu_context_handle context,
uint32_t bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no)
{
union drm_amdgpu_cs cs = {0};
uint64_t *chunk_array;
int i, r;
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
for (i = 0; i < num_chunks; i++)
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
cs.in.ctx_id = context->id;
cs.in.bo_list_handle = bo_list_handle;
cs.in.num_chunks = num_chunks;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
&cs, sizeof(cs));
if (!r && seq_no)
*seq_no = cs.out.handle;
return r;
}
drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
struct drm_amdgpu_cs_chunk_data *data)
{
......
......@@ -60,16 +60,16 @@ struct gralloc_handle_t {
uint32_t usage; /* android libhardware usage flags */
uint32_t stride; /* the stride in bytes */
uint64_t modifier; /* buffer modifiers */
int data_owner; /* owner of data (for validation) */
uint64_t modifier __attribute__((aligned(8))); /* buffer modifiers */
union {
void *data; /* pointer to struct gralloc_gbm_bo_t */
uint64_t reserved;
} __attribute__((aligned(8)));
};
#define GRALLOC_HANDLE_VERSION 3
#define GRALLOC_HANDLE_VERSION 4
#define GRALLOC_HANDLE_MAGIC 0x60585350
#define GRALLOC_HANDLE_NUM_FDS 1
#define GRALLOC_HANDLE_NUM_INTS ( \
......
......@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
[2.4.96],
[2.4.98],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
......@@ -541,7 +541,7 @@ else
AC_DEFINE(HAVE_VISIBILITY, 0)
fi
CFLAGS="$CFLAGS -include config.h"
CPPFLAGS="$CPPFLAGS -include config.h"
AC_SUBST(WARN_CFLAGS)
AC_CONFIG_FILES([
......
......@@ -4,6 +4,10 @@
# device_id, revision_id, product_name <-- single tab after comma
1.0.0
15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
6600, 0, AMD Radeon HD 8600/8700M
6600, 81, AMD Radeon (TM) R7 M370
6601, 0, AMD Radeon (TM) HD 8500M/8700M
......@@ -41,6 +45,7 @@
6665, 83, AMD Radeon (TM) R5 M320
6667, 0, AMD Radeon R5 M200 Series
666F, 0, AMD Radeon HD 8500M
66AF, C1, AMD Radeon VII
6780, 0, ATI FirePro V (FireGL V) Graphics Adapter
678A, 0, ATI FirePro V (FireGL V) Graphics Adapter
6798, 0, AMD Radeon HD 7900 Series
......@@ -63,9 +68,12 @@
67DF, C7, AMD Radeon (TM) RX 480 Graphics
67DF, CF, AMD Radeon (TM) RX 470 Graphics
67DF, D7, Radeon(TM) RX 470 Graphics
67DF, E0, Radeon RX 470 Series
67DF, E1, Radeon RX 590 Series
67DF, E3, Radeon RX Series
67DF, E7, Radeon RX 580 Series
67DF, EF, Radeon RX 570 Series
67DF, F7, Radeon RX P30PH
67C2, 01, AMD Radeon (TM) Pro V7350x2
67C2, 02, AMD Radeon (TM) Pro V7300X
67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
......@@ -85,6 +93,7 @@
67EF, C5, AMD Radeon (TM) RX 460 Graphics
67EF, C7, AMD Radeon (TM) RX Graphics
67EF, CF, AMD Radeon (TM) RX 460 Graphics
67EF, E2, RX 560X
67EF, E0, Radeon RX 560 Series
67EF, E1, Radeon RX Series
67EF, E3, Radeon RX Series
......@@ -127,21 +136,23 @@
683D, 0, AMD Radeon HD 7700 Series
683F, 0, AMD Radeon HD 7700 Series
6860, 00, Radeon Instinct MI25
6860, 01, Radeon Pro V320
6860, 01, Radeon Instinct MI25
6860, 02, Radeon Instinct MI25
6860, 03, Radeon Pro V340
6860, 04, Radeon Instinct MI25x2
6861, 00, Radeon(TM) Pro WX9100
6861, 00, Radeon Pro WX 9100
6862, 00, Radeon Pro SSG
6863, 00, Radeon Vega Frontier Edition
6864, 03, Radeon Pro V340
6864, 04, Instinct MI25x2
6868, 00, Radeon(TM) Pro WX8100
686C, 00, GLXT (Radeon Instinct MI25) MxGPU VFID
686C, 01, GLXT (Radeon Pro V320) MxGPU
686C, 02, GLXT (Radeon Instinct MI25) MxGPU
686C, 03, GLXT (Radeon Pro V340) MxGPU
686C, 04, GLXT (Radeon Instinct MI25x2) MxGPU
6868, 00, Radeon (TM) PRO WX 8200
686C, 00, Radeon Instinct MI25 MxGPU
686C, 01, Radeon Instinct MI25 MxGPU
686C, 02, Radeon Instinct MI25 MxGPU
686C, 03, Radeon Pro V340 MxGPU
686C, 04, Radeon Instinct MI25x2 MxGPU
686C, 05, Radeon Pro V340L MxGPU
686C, 06, Radeon Instinct MI25 MxGPU
687F, C0, Radeon RX Vega
687F, C1, Radeon RX Vega
687F, C3, Radeon RX Vega
......@@ -165,12 +176,15 @@
6980, 00, Radeon Pro WX3100
6985, 00, AMD Radeon Pro WX3100
6987, 80, AMD Embedded Radeon E9171
6987, C0, Radeon 550X Series
6987, C3, Radeon 540X Series
6995, 00, AMD Radeon Pro WX2100
6997, 00, Radeon Pro WX2100
699F, 81, AMD Embedded Radeon E9170 Series
699F, C0, Radeon 500 Series
699F, C1, Radeon 540 Series
699F, C3, Radeon 500 Series
699F, C7, Radeon RX 550 Series
699F, C7, Radeon 550 Series
7300, C1, AMD FirePro (TM) S9300 x2
7300, C8, AMD Radeon (TM) R9 Fury Series
7300, C9, Radeon (TM) Pro Duo
......@@ -185,3 +199,4 @@
9874, 87, AMD Radeon R5 Graphics
9874, 85, AMD Radeon R6 Graphics
9874, 84, AMD Radeon R7 Graphics
6FDF, EF, AMD Radeon RX 580 2048SP
......@@ -150,7 +150,7 @@ struct etna_cmd_stream_priv {
struct etna_bo **bos;
uint32_t nr_bos, max_bos;
/* notify callback if buffer reset happend */
/* notify callback if buffer reset happened */
void (*reset_notify)(struct etna_cmd_stream *stream, void *priv);
void *reset_notify_priv;
};
......
......@@ -276,7 +276,7 @@ drm_public uint32_t exynos_bo_handle(struct exynos_bo *bo)
* @bo: a exynos buffer object including a gem object handle to be mmapped
* to user space.
*
* if true, user pointer mmaped else NULL.
* if true, user pointer mmapped else NULL.
*/
drm_public void *exynos_bo_map(struct exynos_bo *bo)
{
......
......@@ -64,7 +64,7 @@ struct drm_exynos_gem_info {
/**
* A structure for user connection request of virtual display.
*
* @connection: indicate whether doing connetion or not by user.
* @connection: indicate whether doing connection or not by user.
* @extensions: if this value is 1 then the vidi driver would need additional
* 128bytes edid data.
* @edid: the edid data pointer from user side.
......
......@@ -46,7 +46,7 @@ struct exynos_device {
* @handle: a gem handle to gem object created.
* @flags: indicate memory allocation and cache attribute types.
* @size: size to the buffer created.
* @vaddr: user space address to a gem buffer mmaped.
* @vaddr: user space address to a gem buffer mmapped.
* @name: a gem global handle from flink request.
*/
struct exynos_bo {
......
This is a historical discription of what is now the kgsl backend
This is a historical description of what is now the kgsl backend
in libdrm freedreno (before the upstream drm/msm driver). Note
that the kgsl backend requires the "kgsl-drm" shim driver, which
usually is in disrepair (QCOM does not build it for android), and
......
......@@ -74,7 +74,7 @@ struct msm_ringbuffer {
/* should have matching entries in submit.cmds: */
DECLARE_ARRAY(struct msm_cmd *, cmds);
/* List of physical cmdstream buffers (msm_cmd) assocated with this
/* List of physical cmdstream buffers (msm_cmd) associated with this
* logical fd_ringbuffer.
*
* Note that this is different from msm_ringbuffer::cmds (which
......
......@@ -204,12 +204,15 @@ union drm_amdgpu_bo_list {
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
/* indicate gpu reset occured after ctx created */
/* indicate gpu reset occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
/* indicate vram lost occured after ctx created */
/* indicate vram lost occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
/* indicate some errors are detected by RAS */
#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
/* Context priority level */
#define AMDGPU_CTX_PRIORITY_UNSET -2048
......@@ -272,13 +275,14 @@ union drm_amdgpu_vm {
/* sched ioctl */
#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32 op;
__u32 fd;
__s32 priority;
__u32 flags;
__u32 ctx_id;
};
union drm_amdgpu_sched {
......@@ -326,6 +330,12 @@ struct drm_amdgpu_gem_userptr {
/* GFX9 and later: */
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
......@@ -517,6 +527,7 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
......@@ -559,6 +570,11 @@ union drm_amdgpu_cs {
* caches (L2/vL1/sL1/I$). */
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
* This will reset wave ID counters for the IB.
*/
#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
......@@ -665,6 +681,9 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
/* Subquery id: Query GFX RLC SRLS firmware version */
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
/* Subquery id: Query DMCU firmware version */
#define AMDGPU_INFO_FW_DMCU 0x12
#define AMDGPU_INFO_FW_TA 0x13
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
/* the used VRAM size */
......@@ -718,6 +737,37 @@ struct drm_amdgpu_cs_chunk_data {
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
/* query ras mask of enabled features*/
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
/* RAS MASK: UMC (VRAM) */
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
/* RAS MASK: SDMA */
#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
/* RAS MASK: GFX */
#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
/* RAS MASK: MMHUB */
#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
/* RAS MASK: ATHUB */
#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
/* RAS MASK: PCIE */
#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
/* RAS MASK: HDP */
#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
/* RAS MASK: XGMI */
#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
/* RAS MASK: DF */
#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
/* RAS MASK: SMN */
#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
/* RAS MASK: SEM */
#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
/* RAS MASK: MP0 */
#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
/* RAS MASK: MP1 */
#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
/* RAS MASK: FUSE */
#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
......
......@@ -729,8 +729,18 @@ struct drm_syncobj_handle {
__u32 pad;
};
struct drm_syncobj_transfer {
__u32 src_handle;
__u32 dst_handle;
__u64 src_point;
__u64 dst_point;
__u32 flags;
__u32 pad;
};
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
struct drm_syncobj_wait {
__u64 handles;
/* absolute timeout */
......@@ -741,12 +751,33 @@ struct drm_syncobj_wait {
__u32 pad;
};
struct drm_syncobj_timeline_wait {
__u64 handles;
/* wait on specific timeline point for every handles*/
__u64 points;
/* absolute timeout */
__s64 timeout_nsec;
__u32 count_handles;
__u32 flags;
__u32 first_signaled; /* only valid when not waiting all */
__u32 pad;
};
struct drm_syncobj_array {
__u64 handles;
__u32 count_handles;
__u32 pad;
};
struct drm_syncobj_timeline_array {
__u64 handles;
__u64 points;
__u32 count_handles;
__u32 pad;
};
/* Query current scanout sequence number */
struct drm_crtc_get_sequence {
__u32 crtc_id; /* requested crtc_id */
......@@ -903,6 +934,11 @@ extern "C" {
#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
......
......@@ -144,6 +144,17 @@ extern "C" {
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
/*
* Floating point 64bpp RGB
* IEEE 754-2008 binary16 half-precision float
* [15:0] sign:exponent:mantissa 1:5:10
*/
#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
/* packed YCbCr */
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
......@@ -151,6 +162,52 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
/*
* packed Y2xx indicate for each component, xx valid data occupy msb
* 16-xx padding occupy lsb
*/
#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
/*
* packed Y4xx indicate for each component, xx valid data occupy msb
* 16-xx padding occupy lsb except Y410
*/
#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
/*
* packed YCbCr420 2x2 tiled formats
* first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
*/
/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
/*
* 1-plane YUV 4:2:0
* In these formats, the component ordering is specified (Y, followed by U
* then V), but the exact Linear layout is undefined.
* These formats can only be used with a non-Linear modifier.
*/
#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
/*
* 2 plane RGB + A
......@@ -180,6 +237,34 @@ extern "C" {
#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y:x [10:6] little endian
* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
*/
#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y:x [10:6] little endian
* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
*/
#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y:x [12:4] little endian
* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
*/
#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y little endian
* index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
*/
#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
......@@ -223,6 +308,8 @@ extern "C" {
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
/* add more to the end as needed */
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
......@@ -294,7 +381,7 @@ extern "C" {
* This is a tiled layout using 4Kb tiles in row-major layout.
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
* are arranged in four groups (two wide, two high) with column-major layout.
* Each group therefore consits out of four 256 byte units, which are also laid
* Each group therefore consists out of four 256 byte units, which are also laid
* out as 2x2 column-major.
* 256 byte units are made out of four 64 byte blocks of pixels, producing
* either a square block or a 2:1 unit.
......@@ -338,6 +425,15 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
/*
* Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
*
* This is a simple tiled layout using tiles of 16x16 pixels in a row-major
* layout. For YCbCr formats Cb/Cr components are taken in such a way that
* they correspond to their 16x16 luma block.
*/
#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
/*
* Qualcomm Compressed Format
*
......@@ -548,6 +644,9 @@ extern "C" {
* AFBC has several features which may be supported and/or used, which are
* represented using bits in the modifier. Not all combinations are valid,
* and different devices or use-cases may support different combinations.
*
* Further information on the use of AFBC modifiers can be found in
* Documentation/gpu/afbc.rst
*/
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
......@@ -557,10 +656,18 @@ extern "C" {
* Indicates the superblock size(s) used for the AFBC buffer. The buffer
* size (in pixels) must be aligned to a multiple of the superblock size.
* Four lowest significant bits(LSBs) are reserved for block size.
*
* Where one superblock size is specified, it applies to all planes of the
* buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
* the first applies to the Luma plane and the second applies to the Chroma
* plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
* Multiple superblock sizes are only valid for multi-plane YCbCr formats.
*/
#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
/*
* AFBC lossless colorspace transform
......@@ -620,6 +727,35 @@ extern "C" {
*/
#define AFBC_FORMAT_MOD_SC (1ULL << 9)
/*
* AFBC double-buffer
*
* Indicates that the buffer is allocated in a layout safe for front-buffer
* rendering.
*/
#define AFBC_FORMAT_MOD_DB (1ULL << 10)
/*
* AFBC buffer content hints
*
* Indicates that the buffer includes per-superblock content hints.
*/
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
/*
* Allwinner tiled modifier
*
* This tiling mode is implemented by the VPU found on all Allwinner platforms,
* codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
* planes.
*
* With this tiling, the luminance samples are disposed in tiles representing
* 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
* The pixel order in each tile is linear and the tiles are disposed linearly,
* both in row-major order.
*/
#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
#if defined(__cplusplus)
}
#endif
......