1. 17 Dec, 2018 19 commits
    • Kenneth Graunke's avatar
      i965: Don't override subslice count to 4 on Gen11. · 3c71ba3b
      Kenneth Graunke authored
      
      
      Gen9-10 have fewer than 4 subslices per slice, so they need this to be
      rounded up.  Gen11 isn't documented as needing this hack, and it can
      also have more than 4 subslices, so the hack actually can break things.
      Reviewed-by: Anuj Phogat's avatarAnuj Phogat <anuj.phogat@gmail.com>
      3c71ba3b
    • Ian Romanick's avatar
      intel/compiler: More peephole_select for pre-Gen6 · af07141b
      Ian Romanick authored
      
      
      No shader-db changes on any Gen6+ platform.
      
      All of the shaders with cycles hurt by more than ~2% are from Master of
      Orion.  All of the shaders have instructions helped.  It looks like the
      pass enables some control flow to be converted to bcsels, then the
      scheduler does dumb things.  These are new shaders (just added before
      doing this shader-db run), so there's probably some low-hanging fruit.
      
      Iron Lake
      total instructions in shared programs: 8214327 -> 8213684 (<.01%)
      instructions in affected programs: 84469 -> 83826 (-0.76%)
      helped: 114
      HURT: 26
      helped stats (abs) min: 2 max: 18 x̄: 7.75 x̃: 9
      helped stats (rel) min: 0.17% max: 13.73% x̄: 2.52% x̃: 1.05%
      HURT stats (abs)   min: 2 max: 20 x̄: 9.23 x̃: 8
      HURT stats (rel)   min: 0.70% max: 2.48% x̄: 1.66% x̃: 1.61%
      95% mean confidence interval for instructions value: -5.87 -3.32
      95% mean confidence interval for instructions %-change: -2.32% -1.17%
      Instructions are helped.
      
      total cycles in shared programs: 187736850 -> 187749314 (<.01%)
      cycles in affected programs: 506750 -> 519214 (2.46%)
      helped: 104
      HURT: 36
      helped stats (abs) min: 2 max: 72 x̄: 21.96 x̃: 16
      helped stats (rel) min: 0.02% max: 6.16% x̄: 0.97% x̃: 0.63%
      HURT stats (abs)   min: 4 max: 1402 x̄: 409.67 x̃: 40
      HURT stats (rel)   min: 0.33% max: 23.12% x̄: 5.79% x̃: 1.39%
      95% mean confidence interval for cycles value: 28.32 149.74
      95% mean confidence interval for cycles %-change: -0.07% 1.61%
      Inconclusive result (%-change mean confidence interval includes 0).
      
      GM45
      total instructions in shared programs: 5044014 -> 5043652 (<.01%)
      instructions in affected programs: 46751 -> 46389 (-0.77%)
      helped: 63
      HURT: 13
      helped stats (abs) min: 2 max: 29 x̄: 7.65 x̃: 9
      helped stats (rel) min: 0.17% max: 13.73% x̄: 2.93% x̃: 1.04%
      HURT stats (abs)   min: 2 max: 20 x̄: 9.23 x̃: 8
      HURT stats (rel)   min: 0.66% max: 2.35% x̄: 1.58% x̃: 1.52%
      95% mean confidence interval for instructions value: -6.54 -2.99
      95% mean confidence interval for instructions %-change: -3.04% -1.28%
      Instructions are helped.
      
      total cycles in shared programs: 128143042 -> 128150188 (<.01%)
      cycles in affected programs: 324564 -> 331710 (2.20%)
      helped: 57
      HURT: 19
      helped stats (abs) min: 6 max: 74 x̄: 30.70 x̃: 32
      helped stats (rel) min: 0.08% max: 4.74% x̄: 1.22% x̃: 0.81%
      HURT stats (abs)   min: 10 max: 1400 x̄: 468.21 x̃: 60
      HURT stats (rel)   min: 0.56% max: 19.94% x̄: 5.80% x̃: 1.70%
      95% mean confidence interval for cycles value: 6.90 181.15
      95% mean confidence interval for cycles %-change: -0.52% 1.59%
      Inconclusive result (%-change mean confidence interval includes 0).
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Acked-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      af07141b
    • Ian Romanick's avatar
      nir/opt_peephole_select: Don't peephole_select expensive math instructions · 378f9967
      Ian Romanick authored
      
      
      On some GPUs, especially older Intel GPUs, some math instructions are
      very expensive.  On those architectures, don't reduce flow control to a
      csel if one of the branches contains one of these expensive math
      instructions.
      
      This prevents a bunch of cycle count regressions on pre-Gen6 platforms
      with a later patch (intel/compiler: More peephole select for pre-Gen6).
      
      v2: Remove stray #if block.  Noticed by Thomas.
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Thomas Helland's avatarThomas Helland <thomashelland90@gmail.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      378f9967
    • Ian Romanick's avatar
      intel/compiler: More peephole select · 8fb8ebfb
      Ian Romanick authored
      
      
      Shader-db results:
      
      The one shader hurt for instructions is a compute shader that had both
      spills and fills hurt.
      
      v2: Fix typo in comment noticed by Caio.
      
      v3: Fix inverted condition in brw_nir.c.  Noticed by Lionel.
      
      Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
      total instructions in shared programs: 15072761 -> 15047884 (-0.17%)
      instructions in affected programs: 895539 -> 870662 (-2.78%)
      helped: 3623
      HURT: 1
      helped stats (abs) min: 1 max: 181 x̄: 6.89 x̃: 4
      helped stats (rel) min: 0.10% max: 25.00% x̄: 3.93% x̃: 3.20%
      HURT stats (abs)   min: 92 max: 92 x̄: 92.00 x̃: 92
      HURT stats (rel)   min: 1.92% max: 1.92% x̄: 1.92% x̃: 1.92%
      95% mean confidence interval for instructions value: -7.10 -6.63
      95% mean confidence interval for instructions %-change: -4.03% -3.82%
      Instructions are helped.
      
      total cycles in shared programs: 369738930 -> 369535732 (-0.05%)
      cycles in affected programs: 68027851 -> 67824653 (-0.30%)
      helped: 2609
      HURT: 1035
      helped stats (abs) min: 1 max: 4508 x̄: 181.44 x̃: 77
      helped stats (rel) min: <.01% max: 71.31% x̄: 9.14% x̃: 5.47%
      HURT stats (abs)   min: 1 max: 33336 x̄: 261.04 x̃: 20
      HURT stats (rel)   min: <.01% max: 47.61% x̄: 2.93% x̃: 1.47%
      95% mean confidence interval for cycles value: -96.43 -15.09
      95% mean confidence interval for cycles %-change: -6.07% -5.36%
      Cycles are helped.
      
      total spills in shared programs: 10158 -> 10159 (<.01%)
      spills in affected programs: 166 -> 167 (0.60%)
      helped: 1
      HURT: 1
      
      total fills in shared programs: 22105 -> 22116 (0.05%)
      fills in affected programs: 837 -> 848 (1.31%)
      helped: 4
      HURT: 1
      
      Ivy Bridge
      total instructions in shared programs: 12021190 -> 11990256 (-0.26%)
      instructions in affected programs: 910561 -> 879627 (-3.40%)
      helped: 3344
      HURT: 18
      helped stats (abs) min: 1 max: 99 x̄: 9.29 x̃: 6
      helped stats (rel) min: 0.11% max: 31.18% x̄: 5.19% x̃: 3.31%
      HURT stats (abs)   min: 2 max: 20 x̄: 7.89 x̃: 6
      HURT stats (rel)   min: 0.70% max: 2.59% x̄: 1.63% x̃: 1.70%
      95% mean confidence interval for instructions value: -9.49 -8.91
      95% mean confidence interval for instructions %-change: -5.32% -4.98%
      Instructions are helped.
      
      total cycles in shared programs: 179077826 -> 178570196 (-0.28%)
      cycles in affected programs: 63205667 -> 62698037 (-0.80%)
      helped: 2767
      HURT: 620
      helped stats (abs) min: 1 max: 7531 x̄: 217.58 x̃: 88
      helped stats (rel) min: <.01% max: 75.86% x̄: 9.59% x̃: 6.09%
      HURT stats (abs)   min: 1 max: 31255 x̄: 152.27 x̃: 11
      HURT stats (rel)   min: <.01% max: 36.36% x̄: 2.77% x̃: 0.58%
      95% mean confidence interval for cycles value: -173.94 -125.81
      95% mean confidence interval for cycles %-change: -7.68% -6.97%
      Cycles are helped.
      
      Sandy Bridge
      total instructions in shared programs: 10852569 -> 10843758 (-0.08%)
      instructions in affected programs: 235803 -> 226992 (-3.74%)
      helped: 800
      HURT: 0
      helped stats (abs) min: 1 max: 88 x̄: 11.01 x̃: 8
      helped stats (rel) min: 0.11% max: 23.08% x̄: 4.69% x̃: 3.36%
      95% mean confidence interval for instructions value: -11.93 -10.10
      95% mean confidence interval for instructions %-change: -4.99% -4.39%
      Instructions are helped.
      
      total cycles in shared programs: 154732047 -> 154608941 (-0.08%)
      cycles in affected programs: 4063110 -> 3940004 (-3.03%)
      helped: 606
      HURT: 253
      helped stats (abs) min: 1 max: 2524 x̄: 227.93 x̃: 62
      helped stats (rel) min: 0.02% max: 39.24% x̄: 4.36% x̃: 1.81%
      HURT stats (abs)   min: 1 max: 1966 x̄: 59.36 x̃: 11
      HURT stats (rel)   min: 0.02% max: 67.10% x̄: 3.22% x̃: 0.67%
      95% mean confidence interval for cycles value: -170.49 -116.13
      95% mean confidence interval for cycles %-change: -2.61% -1.65%
      Cycles are helped.
      
      No change on Iron Lake or GM45.
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      8fb8ebfb
    • Ian Romanick's avatar
      nir/opt_peephole_select: Don't try to remove flow control around indirect loads · 09b7e1d8
      Ian Romanick authored
      
      
      That flow control may be trying to avoid invalid loads.  On at least
      some platforms, those loads can also be expensive.
      
      No shader-db changes on any Intel platform (even with the later patch
      "intel/compiler: More peephole select").
      
      v2: Add a 'indirect_load_ok' flag to nir_opt_peephole_select.  Suggested
      by Rob.  See also the big comment in src/intel/compiler/brw_nir.c.
      
      v3: Use nir_deref_instr_has_indirect instead of deref_has_indirect (from
      nir_lower_io_arrays_to_elements.c).
      
      v4: Fix inverted condition in brw_nir.c.  Noticed by Lionel.
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      09b7e1d8
    • Ian Romanick's avatar
      i965/vec4: Propagate conditional modifiers from more compares to other compares · 4cd1a0be
      Ian Romanick authored
      
      
      If there is a CMP.NZ that compares a single component (via a .zzzz
      swizzle, for example) with 0, it can propagate its conditional modifier
      back to a previous CMP that writes only that component.  The specific
      case that I saw was:
      
          cmp.l.f0(8)     g42<1>.xF       g61<4>.xF       (abs)g18<4>.zF
          ...
          cmp.nz.f0(8)    null<1>D        g42<4>.xD       0D
      
      In this case we can just delete the second CMP.
      
      No changes on Broadwell or Skylake because they do not use the vec4
      backend.  Also no changes on GM45 or Iron Lake.
      
      Sandy Bridge, Ivy Bridge, and Haswell had similar results. (Sandy Bridge shown)
      total instructions in shared programs: 10856676 -> 10852569 (-0.04%)
      instructions in affected programs: 228322 -> 224215 (-1.80%)
      helped: 1331
      HURT: 0
      helped stats (abs) min: 1 max: 7 x̄: 3.09 x̃: 4
      helped stats (rel) min: 0.11% max: 6.67% x̄: 1.88% x̃: 1.83%
      95% mean confidence interval for instructions value: -3.19 -2.99
      95% mean confidence interval for instructions %-change: -1.93% -1.83%
      Instructions are helped.
      
      total cycles in shared programs: 154788865 -> 154732047 (-0.04%)
      cycles in affected programs: 2485892 -> 2429074 (-2.29%)
      helped: 1097
      HURT: 59
      helped stats (abs) min: 2 max: 168 x̄: 51.96 x̃: 64
      helped stats (rel) min: 0.12% max: 12.70% x̄: 3.44% x̃: 2.22%
      HURT stats (abs)   min: 2 max: 16 x̄: 3.02 x̃: 2
      HURT stats (rel)   min: 0.18% max: 0.83% x̄: 0.64% x̃: 0.71%
      95% mean confidence interval for cycles value: -51.04 -47.26
      95% mean confidence interval for cycles %-change: -3.40% -3.07%
      Cycles are helped.
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      4cd1a0be
    • Ian Romanick's avatar
      i965/fs: Eliminate unary op on operand of compare-with-zero · 9a83c3d3
      Ian Romanick authored
      
      
      The (-abs(x) >= 0) => (x == 0) optimization is removed from the vec4 and
      scalar parts. In the VS part, adding the new pattern was not
      helpful. The pattern that is removed is really old, and it has been
      handled by NIR for ages.
      
      All Gen7+ platforms had similar results. (Broadwell shown)
      total instructions in shared programs: 14715715 -> 14715709 (<.01%)
      instructions in affected programs: 474 -> 468 (-1.27%)
      helped: 6
      HURT: 0
      helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
      helped stats (rel) min: 1.12% max: 1.35% x̄: 1.28% x̃: 1.35%
      95% mean confidence interval for instructions value: -1.00 -1.00
      95% mean confidence interval for instructions %-change: -1.40% -1.15%
      Instructions are helped.
      
      total cycles in shared programs: 559569911 -> 559569809 (<.01%)
      cycles in affected programs: 5963 -> 5861 (-1.71%)
      helped: 6
      HURT: 0
      helped stats (abs) min: 16 max: 18 x̄: 17.00 x̃: 17
      helped stats (rel) min: 1.45% max: 1.88% x̄: 1.73% x̃: 1.85%
      95% mean confidence interval for cycles value: -18.15 -15.85
      95% mean confidence interval for cycles %-change: -1.95% -1.51%
      Cycles are helped.
      
      Iron Lake and Sandy Bridge had similar results. (Iron Lake shown)
      total instructions in shared programs: 7780915 -> 7780913 (<.01%)
      instructions in affected programs: 246 -> 244 (-0.81%)
      helped: 2
      HURT: 0
      
      total cycles in shared programs: 177876108 -> 177876106 (<.01%)
      cycles in affected programs: 3636 -> 3634 (-0.06%)
      helped: 1
      HURT: 0
      
      GM45
      total instructions in shared programs: 4799152 -> 4799151 (<.01%)
      instructions in affected programs: 126 -> 125 (-0.79%)
      helped: 1
      HURT: 0
      
      total cycles in shared programs: 122052654 -> 122052652 (<.01%)
      cycles in affected programs: 3640 -> 3638 (-0.05%)
      helped: 1
      HURT: 0
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      9a83c3d3
    • Ian Romanick's avatar
      i965/vec4/dce: Don't narrow the write mask if the flags are used · 440c0513
      Ian Romanick authored
      
      
      In an instruction sequence like
      
                  cmp(8).ge.f0.0 vgrf17:D, vgrf2.xxxx:D, vgrf9.xxxx:D
          (+f0.0) sel(8) vgrf1:UD, vgrf8.xyzw:UD, vgrf1.xyzw:UD
      
      The other fields of vgrf17 may be unused, but the CMP still needs to
      generate the other flag bits.
      
      To my surprise, nothing in shader-db or any test suite appears to hit
      this.  However, I have a change to brw_vec4_cmod_propagation that
      creates cases where this can happen.  This fix prevents a couple dozen
      regressions in that patch.
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Fixes: 5df88c20 ("i965/vec4: Rewrite dead code elimination to use live in/out.")
      440c0513
    • Ian Romanick's avatar
      i965/vec4: Silence unused parameter warnings in vec4 compiler tests · 111bcc8d
      Ian Romanick authored
      
      
      src/intel/compiler/test_vec4_copy_propagation.cpp: In member function ‘virtual brw::dst_reg* copy_propagation_vec4_visitor::make_reg_for_system_value(int)’:
      src/intel/compiler/test_vec4_copy_propagation.cpp:57:51: warning: unused parameter ‘location’ [-Wunused-parameter]
          virtual dst_reg *make_reg_for_system_value(int location)
                                                         ^~~~~~~~
      src/intel/compiler/test_vec4_copy_propagation.cpp: In member function ‘virtual void copy_propagation_vec4_visitor::emit_urb_write_header(int)’:
      src/intel/compiler/test_vec4_copy_propagation.cpp:77:43: warning: unused parameter ‘mrf’ [-Wunused-parameter]
          virtual void emit_urb_write_header(int mrf)
                                                 ^~~
      src/intel/compiler/test_vec4_copy_propagation.cpp: In member function ‘virtual brw::vec4_instruction* copy_propagation_vec4_visitor::emit_urb_write_opcode(bool)’:
      src/intel/compiler/test_vec4_copy_propagation.cpp:82:57: warning: unused parameter ‘complete’ [-Wunused-parameter]
          virtual vec4_instruction *emit_urb_write_opcode(bool complete)
                                                               ^~~~~~~~
      src/intel/compiler/test_vec4_register_coalesce.cpp: In member function ‘virtual brw::dst_reg* register_coalesce_vec4_visitor::make_reg_for_system_value(int)’:
      src/intel/compiler/test_vec4_register_coalesce.cpp:60:51: warning: unused parameter ‘location’ [-Wunused-parameter]
          virtual dst_reg *make_reg_for_system_value(int location)
                                                         ^~~~~~~~
      src/intel/compiler/test_vec4_register_coalesce.cpp: In member function ‘virtual void register_coalesce_vec4_visitor::emit_urb_write_header(int)’:
      src/intel/compiler/test_vec4_register_coalesce.cpp:80:43: warning: unused parameter ‘mrf’ [-Wunused-parameter]
          virtual void emit_urb_write_header(int mrf)
                                                 ^~~
      src/intel/compiler/test_vec4_register_coalesce.cpp: In member function ‘virtual brw::vec4_instruction* register_coalesce_vec4_visitor::emit_urb_write_opcode(bool)’:
      src/intel/compiler/test_vec4_register_coalesce.cpp:85:57: warning: unused parameter ‘complete’ [-Wunused-parameter]
          virtual vec4_instruction *emit_urb_write_opcode(bool complete)
                                                               ^~~~~~~~
      src/intel/compiler/test_vec4_cmod_propagation.cpp: In member function ‘virtual brw::dst_reg* cmod_propagation_vec4_visitor::make_reg_for_system_value(int)’:
      src/intel/compiler/test_vec4_cmod_propagation.cpp:60:51: warning: unused parameter ‘location’ [-Wunused-parameter]
          virtual dst_reg *make_reg_for_system_value(int location)
                                                         ^~~~~~~~
      src/intel/compiler/test_vec4_cmod_propagation.cpp: In member function ‘virtual void cmod_propagation_vec4_visitor::emit_urb_write_header(int)’:
      src/intel/compiler/test_vec4_cmod_propagation.cpp:85:43: warning: unused parameter ‘mrf’ [-Wunused-parameter]
          virtual void emit_urb_write_header(int mrf)
                                                 ^~~
      src/intel/compiler/test_vec4_cmod_propagation.cpp: In member function ‘virtual brw::vec4_instruction* cmod_propagation_vec4_visitor::emit_urb_write_opcode(bool)’:
      src/intel/compiler/test_vec4_cmod_propagation.cpp:90:57: warning: unused parameter ‘complete’ [-Wunused-parameter]
          virtual vec4_instruction *emit_urb_write_opcode(bool complete)
                                                               ^~~~~~~~
      Signed-off-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      111bcc8d
    • Bas Nieuwenhuizen's avatar
      radv: Fix multiview depth clears · f67dea5e
      Bas Nieuwenhuizen authored
      We were not using the view mask for depth clears, causing only the
      first view to be cleared.
      
      Fixes: 2e86f6b2
      
       "radv: Add multiview clears."
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      f67dea5e
    • Bas Nieuwenhuizen's avatar
      radv: Remove redundant format check. · 9add63a3
      Bas Nieuwenhuizen authored
      
      
      The switch directly after the check has a default case that returns
      NULL too, so the effective return value is not changed. Also this
      check is wrong once we start dealing with formats introduced by an
      extension (e.g. YUV formats).
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      9add63a3
    • Emma Anholt's avatar
      nir: Fix clamping of uints for image store lowering. · 708d8f4d
      Emma Anholt authored and Jason Ekstrand's avatar Jason Ekstrand committed
      I botched some copy-and-paste and clamped to signed int max instead of
      uint max.  Fixes KHR-GL46.shader_image_load_store.multiple-uniforms on
      skl.
      
      Fixes: d3e046e7
      
       ("nir: Pull some of intel's image load/store format
      conversion to nir_format.h")
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      708d8f4d
    • Emma Anholt's avatar
      v3d: Fix the argument type for vir_BRANCH(). · 00e2cbc0
      Emma Anholt authored
      Apparently this has been spewing warnings for Jason's clang, but not my
      gcc.
      00e2cbc0
    • Emma Anholt's avatar
      vc4: Reuse nir_format_convert.h in our blend lowering. · 376054ff
      Emma Anholt authored
      These helpers came along after and have effectively the same
      implementation.
      376054ff
    • Samuel Pitoiset's avatar
      radv: report Vulkan version 1.1.90 for real · 445867c8
      Samuel Pitoiset authored
      I thought the value was correctly propagated, but actually not.
      
      Fixes: 2ac6d55f
      
       ("radv: bump reported version to 1.1.90")
      Signed-off-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      Reviewed-by: Bas Nieuwenhuizen's avatarBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
      445867c8
    • Jason Ekstrand's avatar
      anv,radv: Re-enable VK_EXT_pci_bus_info · cae37311
      Jason Ekstrand authored
      
      
      Now at version 2 with the fixed header.
      Reviewed-by: Samuel Iglesias Gonsálvez's avatarSamuel Iglesias Gonsálvez <siglesias@igalia.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      cae37311
    • Jason Ekstrand's avatar
    • Rhys Perry's avatar
      radv: switch from nir_bcsel to nir_b32csel · ef198e8c
      Rhys Perry authored
      Fixes: 191a1dce
      
       ('nir: Add 1-bit Boolean opcodes')
      Signed-off-by: Rhys Perry's avatarRhys Perry <pendingchaos02@gmail.com>
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      ef198e8c
    • Rhys Perry's avatar
      radv: don't set surf_index for stencil-only images · bba94a3d
      Rhys Perry authored
      Fixes: f8d5b377 ('radv: set cb base tile swizzles for MRT speedups (v4)')
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108116
      
      Signed-off-by: Rhys Perry's avatarRhys Perry <pendingchaos02@gmail.com>
      Reviewed-by: Bas Nieuwenhuizen's avatarBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      bba94a3d
  2. 16 Dec, 2018 21 commits