UAPI Changes: - Revert "drm/i915: Fix DP-MST crtc_mask" to avoid MST regressions (Ville) - Disable set/get_tiling ioctl on Gen12+ as hardware is gone (Daniel) - Add immutable zpos plane properties (Ville) - Report dual-subslice count as subslices for Tigerlake (Daniele) Driver Changes: <TIGERLAKE ENABLING> - Enable HDCP 1.4 and 2.2 on Gen12+ (Ramalingam) - Enable display state buffer (DSB) batch-programming (Animesh) - Add 12 BPC support for Tigerlake (Anusha) - Add maximum resolution supported by PSR2 HW for Tigerlake (Jose) - Only allow PSR2 on supporting transcoders (Jose) - Disable pipes in reverse order to comply with MST for Tigerlake+ (Jose) - Implement Tigerlake DisplayPort training sequence (Jose) - Do not apply WaIncreaseDefaultTLBEntries from Gen12 onwards (Michel) - Reuse Icelake OA context logic for Tigerlake (Michel) - Enable VD HCP/MFX sub-pipe power gating (Michel) - Use separate context for relocations to deal with Tigerlake pre-parser (Daniele) - Enabling DSC on Pipe A for Tigerlake (Madhumitha) - Remove Yf tiling and legacy CCS support starting Tigerlake (Dhinakaran) - Remove PSR link standby support starting Tigerlake (Jose) - Access the right register when handling PSR interruptions (Jose) - Move DP_TP_* registers from port to transcoder for Tigerlake (Lucas) - Disable SAGV for Tigerlake (Lucas) - Reuse Gen11 stolen initialization for Gen12 (Lucas) - Apply FBC WA for Tigerlake too (Jose) - Use engine relative LRIs on context setup for Tigerlake (Mika, Daniele) - Register state context definition for Gen12 (Michel) - Extend MI_SEMAPHORE_WAIT instruction for Tigerlake (Chris) - Disable various Tigerlake features in attempt to have stable CI results (Chris) - Add Tigerlake W/A to disable CPS aware color pipe by setting chicken bit (Radhakrishna) - Add Tigerlake W/A to Enable Small PL for power benefit (Michel) - Add missing DDI clock select during DP init sequence for Tigerlake (Clinton) - Add missing update_active_dpll callback on Tigerlake (Clinton) - Finish modular FIA support on registers for Tigerlake (Jose) - Unify disable and enable phy clock gating functions on Tigerlake (Jose) - Check the UC health of TC controllers after power on (Jose) - Add TigerLake bandwidth checking (Stanislav) - Add Pipe D cursor ctrl register for Gen12 (Ankit) - Add DKL PHY PLL calculations (Lucas, Vandita, Jose) - Add memory type decoding for bandwidth checking (James) </TIGERLAKE ENABLING> - Downgrade Gen7 and Cherryview back to aliasing-ppGTT (Chris) - Limit MST to <= 8bpc once again (Ville) - Restrict the aliasing-ppgtt to the size of the ggtt (Chris) - Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for SKL+ (Chris, Jason) - Whitelist COMMON_SLICE_CHICKEN2 (Kenneth) - Include GTT page-size info in error state (Matt A) - Clear STOP_RING bit on reset (Chris) - Ignore lost CSB completion events (Chris) - Use a high priority wq for nonblocking plane updates (Ville) - Bump up Skylake/Icelake+ display/plane/fb size restrictions (Manasi, Ville) - Update Gen11/Gen12 forcewake ranges from BSpec (Mika, Daniele, Michel) - Allow downscale factor of <3.0 on GLK+ for all formats (Ville) - Add missing Comet Lake PCH PCI ID (Matt) - Fix Gen11 SFC reset flow (Daniele) - Fix YCbCr programming for ILK-IVB,HSW+ (Ville) - Save audio frequency programming state at audio domain suspend (Kai) - Fix DisplayPort DSC BPP calculations (Maarten) - Add hardware readout for FEC (Maarten) - Do not add all planes when checking scalers on GLK+ (Maarten) - Make small joiner RAM buffer size platform-specific (Matt R) - Use per-process HWSP as scratch (Michal Wi) - Match allowed Gen11+ CDCLK values to BSpec (Matt R) - Rework CDCLK code for clarity and table format (Matt R) - Unify CDCLK code to reuse functions (Ville) - Enhance CDCLK sanitization (Matt R) - Preallocate Braswell top-level page directory (Chris) - Make vgpu ppgtt notificaiton as atomic operation (Xiaolin) - Use NOEVICT for first pass on attemping to pin a GGTT mmap (Chris) - Disable PSR if more than one eDP panel is present (Jose) - Make breadcrumb flushes more robust (Chris) - Extend non readable MCR range (Mika) - Protect our local workers against I915_FENCE_TIMEOUT (Chris) - Allow stolen memory (and future local memory) addresses in sg_table (Matt A) - Better organize the disable sequence in atomic_commit_tail() (Manasi) - Fix regression with crtc disable ordering (Maarten) - Add HW Gamma LUT readout (Swati) - Hook up power management code to use intel_gt (Andi) - Rework codebase towards use of intel_gt (Tvrtko) - Remove incorrect BUG_ON for schedule-out (Chris, Vinay) - Cleanup cache coloring code (Matt A) - Flush writes before RING_TAIL update on SNB (Chris) - Perform GGTT restore much earlier during resume (Chris) - Make shrink pinning atomic (Chris) - Make i915_vma.flags atomic for mutex reduction (Chris) - Make sure the gen6 ppgtt is bound before first use without struct mutex (Chris) - Report IOMMU status in debugfs (Chris) - Disable FBC if BIOS reserved memory (stolen) is unavailable (Chris) - Add a paranoid flushes and context reload around GPU reset (Chris) - Skip engine busyness sampling when and where not needed (Tvrtko) - Use GT parked time for estimating RC6 while asleep (Chris) - Get the correct wakeref for reading hotplug registers from debugfs (Arkadiusz) - Only apply a rmw mmio update if the value changes (Chris, Daniele) - Extend Haswell GT1 PSMI workaround to all HSW (Chris) - Only enqueue already completed requests (Chris) - Fix preempt-to-busy interactions of virtual requests (Chris) - Prevent bonded requests from overtaking each other on preemption (Chris) - Mark contents as dirty on a write fault (Chris) - Adjust length of MI_LOAD_REGISTER_REG (Michal Wi) - Don't disable interrupts for intel_engine_breadcrumbs_irq() (Sebastian) - Extract GT render sleep (rc6) management (Andi) - Rework SSEU reporting code (Stuart) - Use correct DSC registers in intel_configure_pps_for_dsc_encoder (Manasi) - Use enum pipe instead of crtc index to track active pipes (Ville) - Enforce irq-off lockdep check for for timeline locks (Chris) - Flush the existing fence before GGTT read/write (Chris) - Keep drm_i915_file_private around under RCU (Chris) - Call dma_set_max_seg_size() to silence spurious warnings (Lyude) - Make engine's batch pool safe for use with virtual engines (Chris) - Align power domain names with port names (Imre) - Parameterize and unify HPD code (Lucas) - Use RCU for unlocked vm_idr lookup (Chris) - Replace obj->pin_global with obj->frontbuffer (Chris) - Rework code to use INTEL_NUM_PIPES() (Jani) - Convert device info num_pipes to pipe_mask (Jani) - Introduce INTEL_DISPLAY_ENABLED() (Jani) - Stop conflating HAS_DISPLAY() and disabled display (Jani) - Modularize i915 modesetting probing/init code (Jani) - Use drm_format_info_is_yuv_semiplanar() instead of rolling own (Ville) - Other display codebase cleanups (Ville) - Other GEM codebase cleanup, lockdep and selftest improvements (Chris) - Future-proof DDC pin mapping to reuse ICP variant (Matt R) - Rewrite timeline handling to be RCU based (Chris) - Define explicit wedged on init reset state (Michal Wi) - Add GuC firmware for Elkhartlake (Daniele) - Update HuC firmware naming convention and bump versions (Anusha) - Extract common code from GuC stop/disable comm (Fernando) - Fix perf kernel-doc formatting for struct members (Anna) - Documentation fixes (Joonas)