Commit 20eb44ad authored by Marek Olšák's avatar Marek Olšák

radeonsi: add support for Vega12

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5425d32f
......@@ -226,4 +226,10 @@ CHIPSET(0x6868, VEGA10)
CHIPSET(0x687F, VEGA10)
CHIPSET(0x686C, VEGA10)
CHIPSET(0x69A0, VEGA12)
CHIPSET(0x69A1, VEGA12)
CHIPSET(0x69A2, VEGA12)
CHIPSET(0x69A3, VEGA12)
CHIPSET(0x69AF, VEGA12)
CHIPSET(0x15DD, RAVEN)
......@@ -114,6 +114,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_POLARIS12:
return "polaris11";
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_RAVEN:
return "gfx900";
default:
......
......@@ -135,6 +135,10 @@ static void addrlib_family_rev_id(enum radeon_family family,
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
break;
case CHIP_VEGA12:
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
......@@ -905,8 +909,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
hin.hTileFlags.pipeAligned = 1;
hin.hTileFlags.rbAligned = 1;
hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
hin.depthFlags = in->flags;
hin.swizzleMode = in->swizzleMode;
hin.unalignedWidth = in->width;
......@@ -967,8 +971,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
dout.pMipInfo = meta_mip_info;
din.dccKeyFlags.pipeAligned = 1;
din.dccKeyFlags.rbAligned = 1;
din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
din.colorFlags = in->flags;
din.resourceType = in->resourceType;
din.swizzleMode = in->swizzleMode;
......@@ -1088,8 +1092,14 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
cin.cMaskFlags.pipeAligned = 1;
cin.cMaskFlags.rbAligned = 1;
if (in->numSamples) {
/* FMASK is always aligned. */
cin.cMaskFlags.pipeAligned = 1;
cin.cMaskFlags.rbAligned = 1;
} else {
cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
}
cin.colorFlags = in->flags;
cin.resourceType = in->resourceType;
cin.unalignedWidth = in->width;
......@@ -1116,6 +1126,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
}
static int gfx9_compute_surface(ADDR_HANDLE addrlib,
const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
......@@ -1196,6 +1207,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
else
AddrSurfInfoIn.numSlices = config->info.array_size;
/* This is propagated to HTILE/DCC/CMASK. */
AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
AddrSurfInfoIn.flags.metaRbUnaligned = 0;
switch (mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
assert(config->info.samples <= 1);
......@@ -1321,6 +1336,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
assert(0);
}
/* Temporary workaround to prevent VM faults and hangs. */
if (info->family == CHIP_VEGA12)
surf->u.gfx9.fmask_size *= 8;
return 0;
}
......@@ -1336,7 +1355,7 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
return r;
if (info->chip_class >= GFX9)
return gfx9_compute_surface(addrlib, config, mode, surf);
return gfx9_compute_surface(addrlib, info, config, mode, surf);
else
return gfx6_compute_surface(addrlib, info, config, mode, surf);
}
......@@ -93,6 +93,7 @@ enum radeon_family {
CHIP_POLARIS11,
CHIP_POLARIS12,
CHIP_VEGA10,
CHIP_VEGA12,
CHIP_RAVEN,
CHIP_LAST,
};
......
......@@ -75,6 +75,7 @@ const char *si_get_family_name(const struct si_screen *sscreen)
case CHIP_POLARIS12: return "AMD POLARIS12";
case CHIP_STONEY: return "AMD STONEY";
case CHIP_VEGA10: return "AMD VEGA10";
case CHIP_VEGA12: return "AMD VEGA12";
case CHIP_RAVEN: return "AMD RAVEN";
default: return "AMD unknown";
}
......
......@@ -828,6 +828,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->dpbb_allowed = true;
} else {
/* Only enable primitive binning on Raven by default. */
/* TODO: Investigate if binning is profitable on Vega12. */
sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
!(sscreen->debug_flags & DBG(NO_DPBB));
}
......@@ -855,6 +856,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->rbplus_allowed =
!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
(sscreen->info.family == CHIP_STONEY ||
sscreen->info.family == CHIP_VEGA12 ||
sscreen->info.family == CHIP_RAVEN);
}
......
......@@ -1675,7 +1675,8 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
(sscreen->info.family == CHIP_STONEY ||
sscreen->info.chip_class >= GFX9)) {
sscreen->info.family == CHIP_VEGA10 ||
sscreen->info.family == CHIP_RAVEN)) {
switch (format) {
case PIPE_FORMAT_ETC1_RGB8:
case PIPE_FORMAT_ETC2_RGB8:
......@@ -5045,6 +5046,7 @@ static void si_init_config(struct si_context *sctx)
switch (sctx->b.family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
pc_lines = 4096;
break;
case CHIP_RAVEN:
......
......@@ -414,6 +414,7 @@ void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state)
switch (sctx->b.family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_RAVEN:
/* Tuned for Raven. Vega might need different values. */
context_states_per_bin = 5;
......
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