Commit 5bcf4795 authored by Nanley Chery's avatar Nanley Chery

intel/blorp: Define the clear value bounds for HiZ clears

Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:

./bin/depthstencil-render-miplevels 146 d=z32f_s8

Jason found this to fix incorrect clearing on SKL.

Fixes: 09948151
       ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")
Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <>
Tested-by: Jason Ekstrand's avatarJason Ekstrand <>
parent 285ebc84
......@@ -1628,6 +1628,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
blorp_emit_3dstate_multisample(batch, params);
/* From the BDW PRM Volume 7, Depth Buffer Clear:
* The clear value must be between the min and max depth values
* (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
* D32_FLOAT, then +/-DENORM values are also allowed.
* Set the bounds to match our hardware limits, [0.0, 1.0].
if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {
assert(params->depth.clear_color.f32[0] >= 0.0f);
assert(params->depth.clear_color.f32[0] <= 1.0f);
/* If we can't alter the depth stencil config and multiple layers are
* involved, the HiZ op will fail. This is because the op requires that a
* new config is emitted for each additional layer.
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