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Some resources like backbuffers are explicitly flushed by the frontend
at the appropriate time, others however won't get flushed explicitly.
Remember those resources when they get emitted as a render buffer and
flush them on a context flush to make their content visible to other
entities sharing the buffer.

We still keep the optimized path for most resources where the frontend
promises to do the flushing for us and only enable implicit flushing
when a buffer handle is exported/imported without the
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH flag set.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Just reclaim a bit of screen real estate, purely cosmetic change.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

surf->base.texture is already assigned earlier via a proper
pipe_resource_reference call. Remove the superfluous assignement.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

dri2_resource_get_param() is called from two different places right now.
Only one of them adds the EXPLICIT_FLUSH hint to the handle usage, which
may disable the optimizations provided by this hint without a reason.

Make sure to always add this hint when appropriate.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

createImageWithModifiers dropped the use flags that were present with
the createImage interface as it was believed at the time that all those
use flags could be expressed as a modifier. This turned out to be untrue,
as there are some use flags like SCANOUT and the BACKBUFFER hint that
won't ever get a eqivalent modifier expression.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Don't lose the use flags when dup'ing an image.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Ported from RadeonSI.

GFX10.3 does it properly.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!7566>

Ported from RadeonSI.

To get optimal LDS usage since the previous change.

Cc: 20.2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!7566>

Ported from RadeonSI.

The restriction was applied too late.

Cc: 20.2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!7566>

Ported from RadeonSI.

Cc: 20.2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!7566>

If set, this bit tells the driver that the buffer will only be
mapped once.

radeonsi uses it to disable its "never unmap buffers" optimisations.

Closes: mesa/mesa#3660Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <mesa/mesa!7428>

Do not destroy pending_mutex or thread_mutex if uninitialized.

Do not use or destroy thread_cond if uninitialized.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <mesa/mesa!7599>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

So we can get rid of the offset adjusment done in pack_variant()
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

src0 and src1 were mixed leading to invalid varying indices. In order to
fix that properly, we first extend load_vary to pass the immediate index
through a dedicated field and add a special boolean. This way, we don't
have to make sure src0 always contains the index, and can instead match
the src numbering defined in ISA.xml.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

It's just clearer to have dedicated fields encoding the fact that the
LD_VAR should be SPECIAL, and another field storing the special var id.

With this change, the source index know matches the ISA.xml definition.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Let the compiler pass the update mode instead of inferring from the
constant value.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

mir_estimate_pressure often underestimates the register pressure,
letting too many registers be used for uniforms, causing RA to fail.

Mitigate this by demoting some uniforms back to explicit loads to free
up work registers if register allocation fails.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7616>

Fix defects reported by Coverity Scan.

Argument cannot be negative (NEGATIVE_RETURNS)
negative_returns: sync_fd is passed to a parameter that cannot be negative.

Fixes: cec0bc73 ("turnip: rework fences to use syncobjs")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <mesa/mesa!7647>

Fix defect reported by Coverity Scan.

Missing break in switch (MISSING_BREAK)
unterminated_case: The case for value SpvOpExecutionMode is not
terminated by a 'break' statement.

Fixes: ee5b46fc ("clover/spirv: support CL_KERNEL_COMPILE_WORK_GROUP_SIZE")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <mesa/mesa!7519>

Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking num_entrypoints suggests that it
may be null, but it has already been dereferenced on all paths
leading to the check.

Fixes: 5bcaa1b9 ("st/va: add encode entrypoint v2")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <mesa/mesa!7360>

We now have NIR opt_large_constants support in place, so we can flip the
switch and get better optimization before lowering to a constant buffer,
but also avoid having constant data mixed in with the shader's uniforms,
which should lower CPU overhead on affected shaders.

Only a few shaders are affected (<.01% impact across shader-db), but for
those the impact is pretty big:

instructions in affected programs: 748 -> 639 (-14.57%)
nops in affected programs: 364 -> 284 (-21.98%)
non-nops in affected programs: 384 -> 355 (-7.55%)
mov in affected programs: 47 -> 27 (-42.55%)
cov in affected programs: 9 -> 6 (-33.33%)
dwords in affected programs: 932 -> 836 (-10.30%)
full in affected programs: 13 -> 14 (7.69%)
constlen in affected programs: 140 -> 64 (-54.29%)
(ss) in affected programs: 14 -> 15 (7.14%)

Part-of: <mesa/mesa!5810>

Right now if the shader indirects on some large constant array, we see NIR
load_consts (usually from the const file) of its contents into general
registers, then indirection on the GPRs.  This often results in register
allocation failures, as it's easy to go beyond the ~256 dwords of
registers per invocation.

By moving the large constants to a UBO, we can load an arbitrary number of
them.  They also can be theoretically moved to the constant reg file (~2k
dwords), though you're unlikely to hit this path without an indirect load
on your large constant, and we don't yet let UBO indirect loads get moved
to constant regs.

This possibly won't work out right if we have 16-bit load_constants, but
without other MRs in flight we won't see 16-bit temps to be lowered to
this.

This allows 2 kerbal-space-program shaders to compile that previously
would fail, and fixes the new dEQP-VK and -GLES2 tests I wrote that
dynamically index a 40-element temporary arra...

If you're loading a 32b word from the const file and doing a cov.u32u16
split to two 16bit values, we can't turn that into a reference of a 16-bit
float value directly from the constbuf, because the
CONSTANT_DEMOTION_ENABLE results in a f2f16 operation on the 32-bit value
that we didn't want.

Part-of: <mesa/mesa!5810>

Just indirect in the caller, which means that I'll be able to pass a
non-resource BO in the large-constants case.

Part-of: <mesa/mesa!5810>

cffdump looks at the following 4 instructions to decide if the shader has
*really* ended, so if we pack data after that (such as turnip's next
stage's shader), it might decode instructions that aren't really part of
the shader.

Part-of: <mesa/mesa!5810>

This is useful for freedreno's intrinsic opt_large_constant lowering,
where we want arrays and struct elements aligned to 16 to avoid generating
lots of extra instructions to extract from the right component.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5810>

It's supposed to be ralloced -- there's not even a shader variant destroy
function for freeing, just ralloc_free() on the ir3_shader_variant or the
parent ir3_shader when you're done!

Fixes: f97acb4b ("freedreno/ir3: disk-cache support")
Part-of: <mesa/mesa!5810>

Motivation is to detect earlier certain bugs that can occur when
missing a check for the stage before using the downcast.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <mesa/mesa!7540>

Unless the non uniform work group extension is supported, this
just aliases workgroupsize, so just do that for now.

Fixes:
CL CTS basic enqueued_local_size
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <mesa/mesa!7642>

fixes CTS 3.0 test_computeinfo
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <mesa/mesa!7642>

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <mesa/mesa!7642>

the real IL code will rewrite this
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <mesa/mesa!7642>