sunxi-clocks-for-4.1

Maxime Ripard

@mripard

f1017969 · clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 · Mar 25, 2015

Allwinner clocks changes for 4.1

The usual round of clock changes for the Allwinner SoCs.

There is nothing really standing out here, but a few changes and fixes, most
notably to allow the AHB clock to be parented to a PLL, instead of the CPU
clock to avoid any AHB rate change due to cpufreq.