sunxi-clocks-for-3.20

Maxime Ripard

@mripard

76820fcf · sunxi: clk: Set sun6i-pll1 n_start = 1 · Jan 25, 2015

Allwinner clock changes for 3.20

The set of clock changes for the 3.20 merge window, with mostly:
  - Some PLL fixes for the A80 and A31
  - The MMC custom phase functions are removed, and moved over to the generic
    phase API.
  - Add the A80 MMC clocks

Some DT changes slipped here as well, to preserve bisectability.