• Thierry Reding's avatar
    gpu: host1x: Set up stream ID table · 6841482b
    Thierry Reding authored
    In order to enable the MMIO path stream ID protection provided by the
    incarnation of host1x found in Tegra186 and later, the host1x must be
    provided with the list of stream ID register offsets for each of its
    clients. Some clients (such as VIC) have multiple stream ID registers
    that are assumed to be contiguous. The host1x is programmed with the
    base offset and a limit which provide the range of registers that the
    host1x needs to monitor for writes.
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    6841482b
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