Commit 3169663a authored by Russell King's avatar Russell King

ARM: sa11x0/pxa: convert OS timer registers to IOMEM

Make the OS timer registers have IOMEM like properities so they can
be passed to readl_relaxed/writel_relaxed() et.al. rather than being
straight volatile dereferences.  Add linux/io.h includes where
required.

linux/io.h includes added to arch/arm/mach-sa1100/cpu-sa1100.c,
 arch/arm/mach-sa1100/jornada720_ssp.c, arch/arm/mach-sa1100/leds-lart.c
 drivers/input/touchscreen/jornada720_ts.c, drivers/pcmcia/sa1100_shannon.c
from Arnd.

This fixes these warnings:

arch/arm/mach-sa1100/time.c: In function 'sa1100_timer_init':
arch/arm/mach-sa1100/time.c:104: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type
arch/arm/mach-pxa/time.c: In function 'pxa_timer_init':
arch/arm/mach-pxa/time.c:126: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent bcccc50c
......@@ -7,17 +7,17 @@
* OS Timer & Match Registers
*/
#define OSMR0 __REG(0x40A00000) /* */
#define OSMR1 __REG(0x40A00004) /* */
#define OSMR2 __REG(0x40A00008) /* */
#define OSMR3 __REG(0x40A0000C) /* */
#define OSMR4 __REG(0x40A00080) /* */
#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
#define OMCR4 __REG(0x40A000C0) /* */
#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
#define OSMR0 io_p2v(0x40A00000) /* */
#define OSMR1 io_p2v(0x40A00004) /* */
#define OSMR2 io_p2v(0x40A00008) /* */
#define OSMR3 io_p2v(0x40A0000C) /* */
#define OSMR4 io_p2v(0x40A00080) /* */
#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
#define OMCR4 io_p2v(0x40A000C0) /* */
#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
#define OSSR_M2 (1 << 2) /* Match status channel 2 */
......
......@@ -77,9 +77,10 @@ static void do_gpio_reset(void)
static void do_hw_reset(void)
{
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 368640; /* ... in 100 ms */
writel_relaxed(OWER_WME, OWER);
writel_relaxed(OSSR_M3, OSSR);
/* ... in 100 ms */
writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
}
void pxa_restart(char mode, const char *cmd)
......
......@@ -35,7 +35,7 @@
static u32 notrace pxa_read_sched_clock(void)
{
return OSCR;
return readl_relaxed(OSCR);
}
......@@ -47,8 +47,8 @@ pxa_ost0_interrupt(int irq, void *dev_id)
struct clock_event_device *c = dev_id;
/* Disarm the compare/match, signal the event. */
OIER &= ~OIER_E0;
OSSR = OSSR_M0;
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
c->event_handler(c);
return IRQ_HANDLED;
......@@ -59,10 +59,10 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
{
unsigned long next, oscr;
OIER |= OIER_E0;
next = OSCR + delta;
OSMR0 = next;
oscr = OSCR;
writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
next = readl_relaxed(OSCR) + delta;
writel_relaxed(next, OSMR0);
oscr = readl_relaxed(OSCR);
return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
}
......@@ -72,15 +72,15 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
OIER &= ~OIER_E0;
OSSR = OSSR_M0;
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
/* initializing, released, or preparing for suspend */
OIER &= ~OIER_E0;
OSSR = OSSR_M0;
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
break;
case CLOCK_EVT_MODE_RESUME:
......@@ -108,8 +108,8 @@ static void __init pxa_timer_init(void)
{
unsigned long clock_tick_rate = get_clock_tick_rate();
OIER = 0;
OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
writel_relaxed(0, OIER);
writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
......@@ -122,7 +122,7 @@ static void __init pxa_timer_init(void)
setup_irq(IRQ_OST0, &pxa_ost0_irq);
clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
clocksource_mmio_readl_up);
clockevents_register_device(&ckevt_pxa_osmr0);
}
......@@ -132,12 +132,12 @@ static unsigned long osmr[4], oier, oscr;
static void pxa_timer_suspend(void)
{
osmr[0] = OSMR0;
osmr[1] = OSMR1;
osmr[2] = OSMR2;
osmr[3] = OSMR3;
oier = OIER;
oscr = OSCR;
osmr[0] = readl_relaxed(OSMR0);
osmr[1] = readl_relaxed(OSMR1);
osmr[2] = readl_relaxed(OSMR2);
osmr[3] = readl_relaxed(OSMR3);
oier = readl_relaxed(OIER);
oscr = readl_relaxed(OSCR);
}
static void pxa_timer_resume(void)
......@@ -151,12 +151,12 @@ static void pxa_timer_resume(void)
if (osmr[0] - oscr < MIN_OSCR_DELTA)
osmr[0] += MIN_OSCR_DELTA;
OSMR0 = osmr[0];
OSMR1 = osmr[1];
OSMR2 = osmr[2];
OSMR3 = osmr[3];
OIER = oier;
OSCR = oscr;
writel_relaxed(osmr[0], OSMR0);
writel_relaxed(osmr[1], OSMR1);
writel_relaxed(osmr[2], OSMR2);
writel_relaxed(osmr[3], OSMR3);
writel_relaxed(oier, OIER);
writel_relaxed(oscr, OSCR);
}
#else
#define pxa_timer_suspend NULL
......
......@@ -362,7 +362,7 @@ static void __init assabet_init(void)
static void __init map_sa1100_gpio_regs( void )
{
unsigned long phys = __PREG(GPLR) & PMD_MASK;
unsigned long virt = io_p2v(phys);
unsigned long virt = (unsigned long)io_p2v(phys);
int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
pmd_t *pmd;
......
......@@ -87,6 +87,7 @@
#include <linux/types.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/io.h>
#include <asm/cputype.h>
......
......@@ -19,6 +19,7 @@
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
......
......@@ -830,14 +830,14 @@
* (read/write).
*/
#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
#define OSSR_M(Nb) /* Match detected [0..3] */ \
(0x00000001 << (Nb))
......
......@@ -24,6 +24,7 @@
#ifndef __ASM_ARCH_SA1100_GPIO_H
#define __ASM_ARCH_SA1100_GPIO_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm-generic/gpio.h>
......
......@@ -32,7 +32,7 @@
#define PIO_START 0x80000000 /* physical start of IO space */
#define io_p2v( x ) \
( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
#define io_v2p( x ) \
( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
......@@ -47,6 +47,8 @@
#define CPU_SA1110_ID (0x6901b110)
#define CPU_SA1110_MASK (0xfffffff0)
#define __MREG(x) IOMEM(io_p2v(x))
#ifndef __ASSEMBLY__
#include <asm/cputype.h>
......@@ -56,7 +58,7 @@
#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
# define __PREG(x) (io_v2p((unsigned long)&(x)))
static inline unsigned long get_clock_tick_rate(void)
......
......@@ -8,6 +8,8 @@
#include "hardware.h"
#define IOMEM(x) (x)
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. We search for the first enabled
......
......@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/syscore_ops.h>
......
......@@ -18,6 +18,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/jornada720.h>
......
......@@ -4,6 +4,7 @@
* Author: ???
*/
#include <linux/init.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/leds.h>
......
......@@ -10,6 +10,7 @@
* pace of the LED.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/leds.h>
......
......@@ -23,6 +23,7 @@
* Storage is local on the stack now.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
......
......@@ -22,7 +22,7 @@
static u32 notrace sa1100_read_sched_clock(void)
{
return OSCR;
return readl_relaxed(OSCR);
}
#define MIN_OSCR_DELTA 2
......@@ -32,8 +32,8 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
struct clock_event_device *c = dev_id;
/* Disarm the compare/match, signal the event. */
OIER &= ~OIER_E0;
OSSR = OSSR_M0;
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
c->event_handler(c);
return IRQ_HANDLED;
......@@ -44,10 +44,10 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
{
unsigned long next, oscr;
OIER |= OIER_E0;
next = OSCR + delta;
OSMR0 = next;
oscr = OSCR;
writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
next = readl_relaxed(OSCR) + delta;
writel_relaxed(next, OSMR0);
oscr = readl_relaxed(OSCR);
return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
}
......@@ -59,8 +59,8 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
OIER &= ~OIER_E0;
OSSR = OSSR_M0;
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
break;
case CLOCK_EVT_MODE_RESUME:
......@@ -86,8 +86,8 @@ static struct irqaction sa1100_timer_irq = {
static void __init sa1100_timer_init(void)
{
OIER = 0;
OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
writel_relaxed(0, OIER);
writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
......@@ -100,7 +100,7 @@ static void __init sa1100_timer_init(void)
setup_irq(IRQ_OST0, &sa1100_timer_irq);
clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
clocksource_mmio_readl_up);
clockevents_register_device(&ckevt_sa1100_osmr0);
}
......@@ -110,26 +110,26 @@ unsigned long osmr[4], oier;
static void sa1100_timer_suspend(void)
{
osmr[0] = OSMR0;
osmr[1] = OSMR1;
osmr[2] = OSMR2;
osmr[3] = OSMR3;
oier = OIER;
osmr[0] = readl_relaxed(OSMR0);
osmr[1] = readl_relaxed(OSMR1);
osmr[2] = readl_relaxed(OSMR2);
osmr[3] = readl_relaxed(OSMR3);
oier = readl_relaxed(OIER);
}
static void sa1100_timer_resume(void)
{
OSSR = 0x0f;
OSMR0 = osmr[0];
OSMR1 = osmr[1];
OSMR2 = osmr[2];
OSMR3 = osmr[3];
OIER = oier;
writel_relaxed(0x0f, OSSR);
writel_relaxed(osmr[0], OSMR0);
writel_relaxed(osmr[1], OSMR1);
writel_relaxed(osmr[2], OSMR2);
writel_relaxed(osmr[3], OSMR3);
writel_relaxed(oier, OIER);
/*
* OSMR0 is the system timer: make sure OSCR is sufficiently behind
*/
OSCR = OSMR0 - LATCH;
writel_relaxed(OSMR0 - LATCH, OSCR);
}
#else
#define sa1100_timer_suspend NULL
......
......@@ -19,6 +19,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/jornada720.h>
......
......@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......
......@@ -54,10 +54,10 @@ static int sa1100dog_open(struct inode *inode, struct file *file)
return -EBUSY;
/* Activate SA1100 Watchdog timer */
OSMR3 = OSCR + pre_margin;
OSSR = OSSR_M3;
OWER = OWER_WME;
OIER |= OIER_E3;
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
writel_relaxed(OSSR_M3, OSSR);
writel_relaxed(OWER_WME, OWER);
writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER);
return nonseekable_open(inode, file);
}
......@@ -80,7 +80,7 @@ static ssize_t sa1100dog_write(struct file *file, const char __user *data,
{
if (len)
/* Refresh OSMR3 timer. */
OSMR3 = OSCR + pre_margin;
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
return len;
}
......@@ -114,7 +114,7 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
break;
case WDIOC_KEEPALIVE:
OSMR3 = OSCR + pre_margin;
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
ret = 0;
break;
......@@ -129,7 +129,7 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
}
pre_margin = oscr_freq * time;
OSMR3 = OSCR + pre_margin;
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
/*fall through*/
case WDIOC_GETTIMEOUT:
......
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