• Thierry Reding's avatar
    gpu: host1x: Restrict IOVA space to DMA mask · 38fabcc9
    Thierry Reding authored
    On Tegra186 and later, the ARM SMMU provides an input address space that
    is 48 bits wide. However, memory clients can only address up to 40 bits.
    If the geometry is used as-is, allocations of IOVA space can end up in a
    region that is not addressable by the memory clients.
    To fix this, restrict the IOVA space to the DMA mask of the host1x
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
dev.c 10.6 KB