dev.c 7.63 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
/*
 * Tegra host1x driver
 *
 * Copyright (c) 2010-2013, NVIDIA Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
20
#include <linux/dma-mapping.h>
21 22 23 24 25 26
#include <linux/io.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/slab.h>
27 28 29

#define CREATE_TRACE_POINTS
#include <trace/events/host1x.h>
30
#undef CREATE_TRACE_POINTS
31

32
#include "bus.h"
33
#include "channel.h"
34
#include "debug.h"
35 36 37
#include "dev.h"
#include "intr.h"

38
#include "hw/host1x01.h"
39
#include "hw/host1x02.h"
40
#include "hw/host1x04.h"
41
#include "hw/host1x05.h"
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
{
	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;

	writel(v, sync_regs + r);
}

u32 host1x_sync_readl(struct host1x *host1x, u32 r)
{
	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;

	return readl(sync_regs + r);
}

57 58 59 60 61 62 63 64 65 66
void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
{
	writel(v, ch->regs + r);
}

u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
{
	return readl(ch->regs + r);
}

67
static const struct host1x_info host1x01_info = {
68 69 70 71 72 73 74
	.nb_channels = 8,
	.nb_pts = 32,
	.nb_mlocks = 16,
	.nb_bases = 8,
	.init = host1x01_init,
	.sync_offset = 0x3000,
	.dma_mask = DMA_BIT_MASK(32),
75 76
};

77 78 79 80 81 82 83
static const struct host1x_info host1x02_info = {
	.nb_channels = 9,
	.nb_pts = 32,
	.nb_mlocks = 16,
	.nb_bases = 12,
	.init = host1x02_init,
	.sync_offset = 0x3000,
84
	.dma_mask = DMA_BIT_MASK(32),
85 86
};

87 88 89 90 91 92 93
static const struct host1x_info host1x04_info = {
	.nb_channels = 12,
	.nb_pts = 192,
	.nb_mlocks = 16,
	.nb_bases = 64,
	.init = host1x04_init,
	.sync_offset = 0x2100,
94
	.dma_mask = DMA_BIT_MASK(34),
95 96
};

97 98 99 100 101 102 103
static const struct host1x_info host1x05_info = {
	.nb_channels = 14,
	.nb_pts = 192,
	.nb_mlocks = 16,
	.nb_bases = 64,
	.init = host1x05_init,
	.sync_offset = 0x2100,
104
	.dma_mask = DMA_BIT_MASK(34),
105 106
};

107
static const struct of_device_id host1x_of_match[] = {
108
	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
109
	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
110
	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
	{ },
};
MODULE_DEVICE_TABLE(of, host1x_of_match);

static int host1x_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct host1x *host;
	struct resource *regs;
	int syncpt_irq;
	int err;

	id = of_match_device(host1x_of_match, &pdev->dev);
	if (!id)
		return -EINVAL;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!regs) {
		dev_err(&pdev->dev, "failed to get registers\n");
		return -ENXIO;
	}

	syncpt_irq = platform_get_irq(pdev, 0);
	if (syncpt_irq < 0) {
137 138
		dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
		return syncpt_irq;
139 140 141 142 143 144
	}

	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
	if (!host)
		return -ENOMEM;

145 146 147
	mutex_init(&host->devices_lock);
	INIT_LIST_HEAD(&host->devices);
	INIT_LIST_HEAD(&host->list);
148 149 150 151 152 153 154 155 156 157
	host->dev = &pdev->dev;
	host->info = id->data;

	/* set common host1x device data */
	platform_set_drvdata(pdev, host);

	host->regs = devm_ioremap_resource(&pdev->dev, regs);
	if (IS_ERR(host->regs))
		return PTR_ERR(host->regs);

158 159
	dma_set_mask_and_coherent(host->dev, host->info->dma_mask);

160 161 162 163 164 165 166 167 168 169 170 171 172
	if (host->info->init) {
		err = host->info->init(host);
		if (err)
			return err;
	}

	host->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(host->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		err = PTR_ERR(host->clk);
		return err;
	}

173 174
	host->rst = devm_reset_control_get(&pdev->dev, "host1x");
	if (IS_ERR(host->rst)) {
175
		err = PTR_ERR(host->rst);
176 177 178 179
		dev_err(&pdev->dev, "failed to get reset: %d\n", err);
		return err;
	}

180 181 182 183 184 185 186 187 188
	if (iommu_present(&platform_bus_type)) {
		struct iommu_domain_geometry *geometry;
		unsigned long order;

		host->domain = iommu_domain_alloc(&platform_bus_type);
		if (!host->domain)
			return -ENOMEM;

		err = iommu_attach_device(host->domain, &pdev->dev);
189 190 191 192 193
		if (err == -ENODEV) {
			iommu_domain_free(host->domain);
			host->domain = NULL;
			goto skip_iommu;
		} else if (err) {
194
			goto fail_free_domain;
195
		}
196 197 198 199 200 201 202 203 204 205

		geometry = &host->domain->geometry;

		order = __ffs(host->domain->pgsize_bitmap);
		init_iova_domain(&host->iova, 1UL << order,
				 geometry->aperture_start >> order,
				 geometry->aperture_end >> order);
		host->iova_end = geometry->aperture_end;
	}

206
skip_iommu:
207 208
	err = host1x_channel_list_init(&host->channel_list,
				       host->info->nb_channels);
209 210
	if (err) {
		dev_err(&pdev->dev, "failed to initialize channel list\n");
211
		goto fail_detach_device;
212 213
	}

214 215 216
	err = clk_prepare_enable(host->clk);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to enable clock\n");
217
		goto fail_free_channels;
218 219
	}

220 221 222 223 224 225
	err = reset_control_deassert(host->rst);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
		goto fail_unprepare_disable;
	}

226 227 228
	err = host1x_syncpt_init(host);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize syncpts\n");
229
		goto fail_reset_assert;
230 231
	}

232 233 234 235 236 237
	err = host1x_intr_init(host, syncpt_irq);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize interrupts\n");
		goto fail_deinit_syncpt;
	}

238 239
	host1x_debug_init(host);

240 241 242
	err = host1x_register(host);
	if (err < 0)
		goto fail_deinit_intr;
243

244
	return 0;
245

246 247
fail_deinit_intr:
	host1x_intr_deinit(host);
248 249
fail_deinit_syncpt:
	host1x_syncpt_deinit(host);
250 251
fail_reset_assert:
	reset_control_assert(host->rst);
252 253
fail_unprepare_disable:
	clk_disable_unprepare(host->clk);
254 255
fail_free_channels:
	host1x_channel_list_free(&host->channel_list);
256 257 258 259 260 261 262 263 264
fail_detach_device:
	if (host->domain) {
		put_iova_domain(&host->iova);
		iommu_detach_device(host->domain, &pdev->dev);
	}
fail_free_domain:
	if (host->domain)
		iommu_domain_free(host->domain);

265
	return err;
266 267
}

268
static int host1x_remove(struct platform_device *pdev)
269 270 271
{
	struct host1x *host = platform_get_drvdata(pdev);

272
	host1x_unregister(host);
273
	host1x_intr_deinit(host);
274
	host1x_syncpt_deinit(host);
275
	reset_control_assert(host->rst);
276 277
	clk_disable_unprepare(host->clk);

278 279 280 281 282 283
	if (host->domain) {
		put_iova_domain(&host->iova);
		iommu_detach_device(host->domain, &pdev->dev);
		iommu_domain_free(host->domain);
	}

284 285 286
	return 0;
}

287
static struct platform_driver tegra_host1x_driver = {
288 289 290 291
	.driver = {
		.name = "tegra-host1x",
		.of_match_table = host1x_of_match,
	},
292 293
	.probe = host1x_probe,
	.remove = host1x_remove,
294 295
};

296 297 298 299 300
static struct platform_driver * const drivers[] = {
	&tegra_host1x_driver,
	&tegra_mipi_driver,
};

301 302 303 304
static int __init tegra_host1x_init(void)
{
	int err;

305
	err = bus_register(&host1x_bus_type);
306 307 308
	if (err < 0)
		return err;

309
	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
310
	if (err < 0)
311
		bus_unregister(&host1x_bus_type);
312

313
	return err;
314 315 316 317 318
}
module_init(tegra_host1x_init);

static void __exit tegra_host1x_exit(void)
{
319
	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
320
	bus_unregister(&host1x_bus_type);
321 322
}
module_exit(tegra_host1x_exit);
323

324
MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
325 326 327
MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
MODULE_DESCRIPTION("Host1x driver for Tegra products");
MODULE_LICENSE("GPL");