i965/fs: Support arbitrarily large sampler state indices on Haswell+.

The message descriptor's "Sampler Index" field is only 4 bits (on all
generations of hardware), so it can only represent indices 0 through 15.

Haswell introduced a new field in the message header - "Sampler State
Pointer".  Normally, this is copied straight from g0, but we can also
add a byte offset (as long as it's a multiple of 32).

This patch uses a "Sampler State Pointer" offset to select a group of
16 sampler states, and then uses the "Sampler Index" field to select
the state within that group.
Signed-off-by: Kenneth Graunke (AFK until mid-April)'s avatarKenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner's avatarMatt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes's avatarChris Forbes <chrisf@ijw.co.nz>
parent d7450e52
......@@ -559,6 +559,23 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
brw_MOV(p, get_element_ud(header_reg, 2),
brw_imm_ud(inst->texture_offset));
}
if (inst->sampler >= 16) {
/* The "Sampler Index" field can only store values between 0 and 15.
* However, we can add an offset to the "Sampler State Pointer"
* field, effectively selecting a different set of 16 samplers.
*
* The "Sampler State Pointer" needs to be aligned to a 32-byte
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
assert(brw->is_haswell); /* field only exists on Haswell */
brw_ADD(p,
get_element_ud(header_reg, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
brw_imm_ud(16 * (inst->sampler / 16) *
sizeof(gen7_sampler_state)));
}
brw_pop_insn_state(p);
}
}
......@@ -573,7 +590,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
inst->base_mrf,
src,
surface_index,
inst->sampler,
inst->sampler % 16,
msg_type,
rlen,
inst->mlen,
......
......@@ -1250,13 +1250,16 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
fs_reg payload = fs_reg(this, glsl_type::float_type);
fs_reg next = payload;
if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf)) {
if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf) || sampler >= 16) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
*
* * ir4_tg4 needs to place its channel select in the header,
* for interaction with ARB_texture_swizzle
*
* The sampler index is only 4-bits, so for larger sampler numbers we
* need to offset the Sampler State Pointer in the header.
*/
header_present = true;
next.reg_offset++;
......
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