Commit 54b95fa8 authored by Kenneth Graunke's avatar Kenneth Graunke
Browse files

iris: Disable aux for sampling/images when disabling it for rendering

When disable_rb_aux_buffer detects that an image is bound for rendering
at the same time that it's bound as a sampler or image view, it flags
that we should disable aux for the render target.  Prior to Tigerlake,
this is all that we need, because the two don't share a common cache
hierarchy.  Sampling can use CCS_E, but rendering uses AUX_NONE.

Tigerlake adds an extra unified L3 cache, which both the sampler and
render caches pull from and add to.  Having the sampler access a surface
with CCS_E while the render cache accesses it with AUX_NONE means that
we introduce cachelines in both modes into the common, shared cache,
which seems to result in rendering corruptions.

To fix this issue, we disable CCS_E for both sampling -and- rendering
on Gfx12+ when a surface is used by both simultaneously.  This means
that sampling loses out on compression in this corner case.

I am unsure if image reads/render writes have the same conflict, since
image access has DC-tagged L3 lines rather than C/Z-tagged L3 lines.
For now, we assume that they do and disable aux out of caution.

Closes: mesa/mesa#7272
parent 27aa1720
Pipeline #708042 waiting for manual action with stages
......@@ -92,6 +92,8 @@ resolve_sampler_views(struct iris_context *ice,
if (info == NULL)
return;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
int i;
BITSET_FOREACH_SET(i, shs->bound_sampler_views, IRIS_MAX_TEXTURES) {
if (!BITSET_TEST(info->textures_used, i))
......@@ -100,16 +102,23 @@ resolve_sampler_views(struct iris_context *ice,
struct iris_sampler_view *isv = shs->textures[i];
if (isv->res->base.b.target != PIPE_BUFFER) {
if (consider_framebuffer) {
bool simultaneous_use = consider_framebuffer &&
disable_rb_aux_buffer(ice, draw_aux_buffer_disabled, isv->res,
isv->view.base_level, isv->view.levels,
"for sampling");
}
iris_resource_prepare_texture(ice, isv->res, isv->view.format,
isv->view.base_level, isv->view.levels,
isv->view.base_array_layer,
isv->view.array_len);
if (simultaneous_use && devinfo->ver >= 12) {
iris_resource_prepare_access(ice, isv->res,
isv->view.base_level, isv->view.levels,
isv->view.base_array_layer,
isv->view.array_len,
ISL_AUX_USAGE_NONE, false);
} else {
iris_resource_prepare_texture(ice, isv->res, isv->view.format,
isv->view.base_level, isv->view.levels,
isv->view.base_array_layer,
isv->view.array_len);
}
}
iris_emit_buffer_barrier_for(batch, isv->res->bo,
......@@ -128,6 +137,8 @@ resolve_image_views(struct iris_context *ice,
if (info == NULL)
return;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
const uint64_t images_used =
(info->images_used[0] | ((uint64_t)info->images_used[1]) << 32);
uint64_t views = shs->bound_image_views & images_used;
......@@ -138,16 +149,16 @@ resolve_image_views(struct iris_context *ice,
struct iris_resource *res = (void *) pview->resource;
if (res->base.b.target != PIPE_BUFFER) {
if (consider_framebuffer) {
unsigned num_layers =
pview->u.tex.last_layer - pview->u.tex.first_layer + 1;
bool simultaneous_use = consider_framebuffer &&
disable_rb_aux_buffer(ice, draw_aux_buffer_disabled,
res, pview->u.tex.level, 1,
"as a shader image");
}
unsigned num_layers =
pview->u.tex.last_layer - pview->u.tex.first_layer + 1;
enum isl_aux_usage aux_usage =
simultaneous_use && devinfo->ver >= 12 ? ISL_AUX_USAGE_NONE :
iris_image_view_aux_usage(ice, pview, info);
iris_resource_prepare_access(ice, res,
......
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