1. 27 Nov, 2018 2 commits
    • Rob Clark's avatar
      freedreno: move ir3 to common location · aa0fed10
      Rob Clark authored
      Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be
      re-used by some future vulkan driver.  The parts that are gallium
      specific have been refactored out and remain in the gallium driver.
      
      Getting the move done now so that it can happen before further
      refactoring to support a6xx specific instructions.
      
      NOTE also removes ir3_cmdline compiler tool from autotools build since
      that was easier than fixing it and I normally use meson build.  Waiting
      patiently for the day that we can remove *everything* from the autotools
      build.
      Signed-off-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
      aa0fed10
    • Rob Clark's avatar
      freedreno/ir3: some header file cleanup · 030e9863
      Rob Clark authored
      Clean up some of the low-hanging-fruit usages of freedreno_util.h
      Signed-off-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
      030e9863
  2. 14 Aug, 2018 1 commit
  3. 05 Mar, 2018 1 commit
    • Rob Clark's avatar
      freedreno/ir3: start dealing with half-precision · 5a5a4307
      Rob Clark authored
      Some instructions, assume src and/or dst is half-precision based on a
      type field (ie. f32/s32/u32 are full precision but others are half
      precision).  So add some code to sanity check the src/dst registers to
      catch mixups.
      
      Also propagate half-precision flag for SSA sources.  The instruction
      consuming a SSA value needs to be of the same type as the one producing
      it.
      
      This is probably not complete half-precision support, but a useful first
      step.  We do still need to add support for nir alu instructions for
      converting between half/full precision.
      Signed-off-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
      5a5a4307
  4. 10 Feb, 2018 3 commits
  5. 12 Nov, 2017 3 commits
    • Rob Clark's avatar
      freedreno/ir3: moar better scheduler · 819a613a
      Rob Clark authored
      Add a new pass that inserts additional dependencies, rather than simply
      relying on SSA srcs added in the nir->ir3 frontend.  This makes it
      easier to deal with barriers, but the additional false deps also lets us
      deal properly with ensuring a write depends on all previous reads.
      
      Since conversion to barrier instructions is lossy (ie. just knowing the
      instruction doesn't tell us enough about what other instructions the
      barrier applies to), use barrier_class/barrier_conflict fields in the
      ir3_instruction to retain this information.
      
      This could probably be relaxed somewhat by considering *which* array/
      buffer/image variable is being referenced.  Ie. a write to buffer A
      can overtake a read from buffer B, if B is not coherent.  (right?)
      Signed-off-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
      819a613a
    • Rob Clark's avatar
      freedreno/ir3: cat6 encoding fixes · 0038deb2
      Rob Clark authored
      Instruction encoding/decoding fixes needed for images, shared variables,
      etc.
      Signed-off-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
      0038deb2
    • Rob Clark's avatar
      freedreno/ir3: add cat7 instructions · 6da51300
      Rob Clark authored
      Needed for memory and execution barriers.
      Signed-off-by: Rob Clark's avatarRob Clark <robdclark@gmail.com>
      6da51300
  6. 04 May, 2017 1 commit
  7. 17 Apr, 2017 1 commit
  8. 14 Apr, 2017 1 commit
  9. 30 Nov, 2016 1 commit
  10. 12 Nov, 2016 1 commit
  11. 31 Oct, 2016 1 commit
  12. 23 Jun, 2016 1 commit
    • Giuseppe Bilotta's avatar
      Remove wrongly repeated words in comments · 60a27ad1
      Giuseppe Bilotta authored
      Clean up misrepetitions ('if if', 'the the' etc) found throughout the
      comments. This has been done manually, after grepping
      case-insensitively for duplicate if, is, the, then, do, for, an,
      plus a few other typos corrected in fly-by
      
      v2:
          * proper commit message and non-joke title;
          * replace two 'as is' followed by 'is' to 'as-is'.
      v3:
          * 'a integer' => 'an integer' and similar (originally spotted by
            Jason Ekstrand, I fixed a few other similar ones while at it)
      Signed-off-by: Giuseppe Bilotta's avatarGiuseppe Bilotta <giuseppe.bilotta@gmail.com>
      Reviewed-by: default avatarChad Versace <chad.versace@intel.com>
      60a27ad1
  13. 02 Jun, 2016 1 commit
  14. 25 Apr, 2016 1 commit
    • Rob Clark's avatar
      freedreno/ir3: convert over to ralloc · 8fe20762
      Rob Clark authored
      The home-grown heap scheme (which is ultra-simple but probably not good
      to always allocate and memset such a chunk of memory up front) was a
      remnant of fdre (where the ir originally came from).  But since we have
      ralloc in mesa, lets just use that instead.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      8fe20762
  15. 24 Apr, 2016 1 commit
  16. 05 Apr, 2016 3 commits
  17. 16 Jan, 2016 2 commits
  18. 27 Jul, 2015 2 commits
  19. 03 Jul, 2015 1 commit
    • Rob Clark's avatar
      freedreno/ir3: fix indirects tracking · 6b9f5cd5
      Rob Clark authored
      cp would update instr->address but not update the indirects array
      resulting in sched getting confused when it had to 'spill' the address
      register.  Add an ir3_instr_set_address() helper to set instr->address
      and also update ir->indirects, and update all places that were writing
      instr->address to use helper instead.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      6b9f5cd5
  20. 30 Jun, 2015 2 commits
  21. 21 Jun, 2015 6 commits
  22. 11 Apr, 2015 1 commit
  23. 05 Apr, 2015 2 commits
  24. 15 Mar, 2015 1 commit