Commit c7d1b52a authored by Kenneth Graunke's avatar Kenneth Graunke

nir: Combine lower_fmod16/32 back into a single lower_fmod.

We originally had a single lower_fmod option.  In commit 2ab2d2e5, Sam
split 32 and 64-bit lowering into separate flags, with the rationale
that some drivers might want different options there.  This left 16-bit
unhandled, so Iago added a lower_fmod16 option in commit ca31df6f.

Now that lower_fmod64 is gone (in favor of nir_lower_doubles and
nir_lower_dmod), we re-combine lower_fmod16 and lower_fmod32 into a
single lower_fmod flag again.  I'm not aware of any hardware which
need lowering for one bitsize and not the other.
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
parent edd45af9
......@@ -2248,8 +2248,7 @@ typedef struct nir_shader_compiler_options {
bool lower_fpow;
bool lower_fsat;
bool lower_fsqrt;
bool lower_fmod16;
bool lower_fmod32;
bool lower_fmod;
/** Lowers ibitfield_extract/ubitfield_extract to ibfe/ubfe. */
bool lower_bitfield_extract;
/** Lowers ibitfield_extract/ubitfield_extract to bfm, compares, shifts. */
......
......@@ -771,9 +771,9 @@ optimizations.extend([
(('bcsel', ('ine', a, -1), ('ifind_msb', a), -1), ('ifind_msb', a)),
# Misc. lowering
(('fmod@16', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b)))), 'options->lower_fmod16'),
(('fmod@32', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b)))), 'options->lower_fmod32'),
(('frem', a, b), ('fsub', a, ('fmul', b, ('ftrunc', ('fdiv', a, b)))), 'options->lower_fmod32'),
(('fmod@16', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b)))), 'options->lower_fmod'),
(('fmod@32', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b)))), 'options->lower_fmod'),
(('frem', a, b), ('fsub', a, ('fmul', b, ('ftrunc', ('fdiv', a, b)))), 'options->lower_fmod'),
(('uadd_carry@32', a, b), ('b2i', ('ult', ('iadd', a, b), a)), 'options->lower_uadd_carry'),
(('usub_borrow@32', a, b), ('b2i', ('ult', a, b)), 'options->lower_usub_borrow'),
......
......@@ -40,7 +40,7 @@ static const nir_shader_compiler_options options = {
.lower_flrp32 = true,
.lower_flrp64 = true,
.lower_ffract = true,
.lower_fmod32 = true,
.lower_fmod = true,
.lower_fdiv = true,
.lower_isign = true,
.lower_ldexp = true,
......@@ -65,7 +65,7 @@ static const nir_shader_compiler_options options_a6xx = {
.lower_flrp32 = true,
.lower_flrp64 = true,
.lower_ffract = true,
.lower_fmod32 = true,
.lower_fmod = true,
.lower_fdiv = true,
.lower_isign = true,
.lower_ldexp = true,
......
......@@ -32,7 +32,7 @@
static const nir_shader_compiler_options options = {
.lower_fpow = true,
.lower_flrp32 = true,
.lower_fmod32 = true,
.lower_fmod = true,
.lower_fdiv = true,
.lower_fceil = true,
.fuse_ffma = true,
......
......@@ -905,7 +905,7 @@ static const nir_shader_compiler_options nir_options = {
.lower_fpow = false,
.lower_fsat = false,
.lower_fsqrt = false, // TODO: only before gm200
.lower_fmod32 = true,
.lower_fmod = true,
.lower_bitfield_extract = false,
.lower_bitfield_extract_to_shifts = false,
.lower_bitfield_insert = false,
......
......@@ -91,7 +91,7 @@ static const nir_shader_compiler_options midgard_nir_options = {
.lower_flrp32 = true,
.lower_flrp64 = true,
.lower_ffract = true,
.lower_fmod32 = true,
.lower_fmod = true,
.lower_fdiv = true,
.lower_idiv = true,
.lower_isign = true,
......
......@@ -34,8 +34,7 @@
.lower_fdiv = true, \
.lower_scmp = true, \
.lower_flrp16 = true, \
.lower_fmod16 = true, \
.lower_fmod32 = true, \
.lower_fmod = true, \
.lower_bitfield_extract = true, \
.lower_bitfield_insert = true, \
.lower_uadd_carry = true, \
......
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