Commit 1d55b0da authored by Connor Abbott's avatar Connor Abbott

radeonsi: Don't force dcc disable for loads

When e9d935ed added force_dcc_off(), we forced it off for any
preloaded image descriptor which had stores associated with them, since
the same preloaded descriptors were used for loads and stores. However,
when the preloading was removed in 16be87c9, the existing logic was
kept despite it not being necessary anymore. The comment above
force_dcc_off() only mentions stores, so only force DCC off for stores.

Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
parent 10895c39
......@@ -997,16 +997,10 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
bool write, bool bindless)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
const struct tgsi_shader_info *info = &ctx->shader->selector->info;
LLVMBuilderRef builder = ctx->ac.builder;
unsigned const_index = base_index + constant_index;
bool dcc_off = write;
/* TODO: images_store and images_atomic are not set */
if (!dynamic_index && image &&
(info->images_store | info->images_atomic) & (1 << const_index))
dcc_off = true;
assert(!descriptor_set);
assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
......
......@@ -218,15 +218,8 @@ image_fetch_rsrc(
bool dcc_off = is_store;
if (!image->Register.Indirect) {
const struct tgsi_shader_info *info = bld_base->info;
unsigned images_writemask = info->images_store |
info->images_atomic;
index = LLVMConstInt(ctx->i32,
si_get_image_slot(image->Register.Index), 0);
if (images_writemask & (1 << image->Register.Index))
dcc_off = true;
} else {
/* From the GL_ARB_shader_image_load_store extension spec:
*
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment