Commit f9a9ba5e authored by Matt Turner's avatar Matt Turner

i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().

Cuts 1.5k of .text.
Reviewed-by: default avatarEmil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
parent 9b978046
......@@ -41,11 +41,6 @@ public:
src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
src_reg();
src_reg(float f);
src_reg(uint32_t u);
src_reg(int32_t i);
src_reg(uint8_t vf[4]);
src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
src_reg(struct brw_reg reg);
bool equals(const src_reg &r) const;
......
......@@ -71,51 +71,6 @@ src_reg::src_reg()
init();
}
src_reg::src_reg(float f)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->f = f;
}
src_reg::src_reg(uint32_t u)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->ud = u;
}
src_reg::src_reg(int32_t i)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->d = i;
}
src_reg::src_reg(uint8_t vf[4])
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
memcpy(&this->ud, vf, sizeof(unsigned));
}
src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
this->ud = (vf0 << 0) | (vf1 << 8) | (vf2 << 16) | (vf3 << 24);
}
src_reg::src_reg(struct brw_reg reg) :
backend_reg(reg)
{
......@@ -382,7 +337,9 @@ vec4_visitor::opt_vector_float()
remaining_channels &= ~inst->dst.writemask;
if (remaining_channels == 0) {
vec4_instruction *mov = MOV(inst->dst, imm);
unsigned vf;
memcpy(&vf, imm, sizeof(vf));
vec4_instruction *mov = MOV(inst->dst, brw_imm_vf(vf));
mov->dst.type = BRW_REGISTER_TYPE_F;
mov->dst.writemask = WRITEMASK_XYZW;
inst->insert_after(block, mov);
......@@ -657,13 +614,13 @@ vec4_visitor::opt_algebraic()
inst->opcode = BRW_OPCODE_MOV;
switch (inst->src[0].type) {
case BRW_REGISTER_TYPE_F:
inst->src[0] = src_reg(0.0f);
inst->src[0] = brw_imm_f(0.0f);
break;
case BRW_REGISTER_TYPE_D:
inst->src[0] = src_reg(0);
inst->src[0] = brw_imm_d(0);
break;
case BRW_REGISTER_TYPE_UD:
inst->src[0] = src_reg(0u);
inst->src[0] = brw_imm_ud(0u);
break;
default:
unreachable("not reached");
......@@ -1232,7 +1189,7 @@ vec4_visitor::eliminate_find_live_channel()
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
if (depth == 0) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[0] = src_reg(0);
inst->src[0] = brw_imm_d(0);
inst->force_writemask_all = true;
progress = true;
}
......@@ -1701,7 +1658,7 @@ vec4_visitor::emit_shader_time_end()
*/
src_reg reset_end = shader_end_time;
reset_end.swizzle = BRW_SWIZZLE_ZZZZ;
vec4_instruction *test = emit(AND(dst_null_d(), reset_end, src_reg(1u)));
vec4_instruction *test = emit(AND(dst_null_ud(), reset_end, brw_imm_ud(1u)));
test->conditional_mod = BRW_CONDITIONAL_Z;
emit(IF(BRW_PREDICATE_NORMAL));
......@@ -1715,12 +1672,12 @@ vec4_visitor::emit_shader_time_end()
* is 2 cycles. Remove that overhead, so I can forget about that when
* trying to determine the time taken for single instructions.
*/
emit(ADD(diff, src_reg(diff), src_reg(-2u)));
emit(ADD(diff, src_reg(diff), brw_imm_ud(-2u)));
emit_shader_time_write(0, src_reg(diff));
emit_shader_time_write(1, src_reg(1u));
emit_shader_time_write(1, brw_imm_ud(1u));
emit(BRW_OPCODE_ELSE);
emit_shader_time_write(2, src_reg(1u));
emit_shader_time_write(2, brw_imm_ud(1u));
emit(BRW_OPCODE_ENDIF);
}
......@@ -1736,7 +1693,7 @@ vec4_visitor::emit_shader_time_write(int shader_time_subindex, src_reg value)
offset.type = BRW_REGISTER_TYPE_UD;
int index = shader_time_index * 3 + shader_time_subindex;
emit(MOV(offset, src_reg(index * SHADER_TIME_STRIDE)));
emit(MOV(offset, brw_imm_d(index * SHADER_TIME_STRIDE)));
time.type = BRW_REGISTER_TYPE_UD;
emit(MOV(time, value));
......
......@@ -484,7 +484,7 @@ namespace brw {
const dst_reg x_times_one_minus_a = vgrf(dst.type);
MUL(y_times_a, y, a);
ADD(one_minus_a, negate(a), src_reg(1.0f));
ADD(one_minus_a, negate(a), brw_imm_f(1.0f));
MUL(x_times_one_minus_a, x, src_reg(one_minus_a));
return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a));
}
......
......@@ -153,7 +153,7 @@ vec4_gs_visitor::emit_prolog()
*/
this->current_annotation = "clear r0.2";
dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, 0u);
vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u));
inst->force_writemask_all = true;
/* Create a virtual register to hold the vertex count */
......@@ -161,7 +161,7 @@ vec4_gs_visitor::emit_prolog()
/* Initialize the vertex_count register to 0 */
this->current_annotation = "initialize vertex_count";
inst = emit(MOV(dst_reg(this->vertex_count), 0u));
inst = emit(MOV(dst_reg(this->vertex_count), brw_imm_ud(0u)));
inst->force_writemask_all = true;
if (c->control_data_header_size_bits > 0) {
......@@ -176,7 +176,7 @@ vec4_gs_visitor::emit_prolog()
*/
if (c->control_data_header_size_bits <= 32) {
this->current_annotation = "initialize control data bits";
inst = emit(MOV(dst_reg(this->control_data_bits), 0u));
inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
inst->force_writemask_all = true;
}
}
......@@ -274,7 +274,7 @@ vec4_gs_visitor::emit_urb_write_header(int mrf)
vec4_instruction *inst = emit(MOV(mrf_reg, r0));
inst->force_writemask_all = true;
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, this->vertex_count,
(uint32_t) gs_prog_data->output_vertex_size_hwords);
brw_imm_ud(gs_prog_data->output_vertex_size_hwords));
}
......@@ -354,11 +354,12 @@ vec4_gs_visitor::emit_control_data_bits()
src_reg dword_index(this, glsl_type::uint_type);
if (urb_write_flags) {
src_reg prev_count(this, glsl_type::uint_type);
emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu));
emit(ADD(dst_reg(prev_count), this->vertex_count,
brw_imm_ud(0xffffffffu)));
unsigned log2_bits_per_vertex =
_mesa_fls(c->control_data_bits_per_vertex);
emit(SHR(dst_reg(dword_index), prev_count,
(uint32_t) (6 - log2_bits_per_vertex)));
brw_imm_ud(6 - log2_bits_per_vertex)));
}
/* Start building the URB write message. The first MRF gets a copy of
......@@ -375,8 +376,9 @@ vec4_gs_visitor::emit_control_data_bits()
* the appropriate OWORD within the control data header.
*/
src_reg per_slot_offset(this, glsl_type::uint_type);
emit(SHR(dst_reg(per_slot_offset), dword_index, 2u));
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset, 1u);
emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u)));
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset,
brw_imm_ud(1u));
}
if (urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS) {
......@@ -388,10 +390,10 @@ vec4_gs_visitor::emit_control_data_bits()
* together.
*/
src_reg channel(this, glsl_type::uint_type);
inst = emit(AND(dst_reg(channel), dword_index, 3u));
inst = emit(AND(dst_reg(channel), dword_index, brw_imm_ud(3u)));
inst->force_writemask_all = true;
src_reg one(this, glsl_type::uint_type);
inst = emit(MOV(dst_reg(one), 1u));
inst = emit(MOV(dst_reg(one), brw_imm_ud(1u)));
inst->force_writemask_all = true;
src_reg channel_mask(this, glsl_type::uint_type);
inst = emit(SHL(dst_reg(channel_mask), one, channel));
......@@ -441,11 +443,11 @@ vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id)
/* reg::sid = stream_id */
src_reg sid(this, glsl_type::uint_type);
emit(MOV(dst_reg(sid), stream_id));
emit(MOV(dst_reg(sid), brw_imm_ud(stream_id)));
/* reg:shift_count = 2 * (vertex_count - 1) */
src_reg shift_count(this, glsl_type::uint_type);
emit(SHL(dst_reg(shift_count), this->vertex_count, 1u));
emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u)));
/* Note: we're relying on the fact that the GEN SHL instruction only pays
* attention to the lower 5 bits of its second source argument, so on this
......@@ -503,8 +505,8 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
* vertex_count & (32 / bits_per_vertex - 1) == 0
*/
vec4_instruction *inst =
emit(AND(dst_null_d(), this->vertex_count,
(uint32_t) (32 / c->control_data_bits_per_vertex - 1)));
emit(AND(dst_null_ud(), this->vertex_count,
brw_imm_ud(32 / c->control_data_bits_per_vertex - 1)));
inst->conditional_mod = BRW_CONDITIONAL_Z;
emit(IF(BRW_PREDICATE_NORMAL));
......@@ -512,7 +514,7 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
/* If vertex_count is 0, then no control data bits have been
* accumulated yet, so we skip emitting them.
*/
emit(CMP(dst_null_d(), this->vertex_count, 0u,
emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u),
BRW_CONDITIONAL_NEQ));
emit(IF(BRW_PREDICATE_NORMAL));
emit_control_data_bits();
......@@ -525,7 +527,7 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
* effect of any call to EndPrimitive() that the shader may have
* made before outputting its first vertex.
*/
inst = emit(MOV(dst_reg(this->control_data_bits), 0u));
inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
inst->force_writemask_all = true;
}
emit(BRW_OPCODE_ENDIF);
......@@ -586,9 +588,9 @@ vec4_gs_visitor::gs_end_primitive()
/* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
src_reg one(this, glsl_type::uint_type);
emit(MOV(dst_reg(one), 1u));
emit(MOV(dst_reg(one), brw_imm_ud(1u)));
src_reg prev_count(this, glsl_type::uint_type);
emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu));
emit(ADD(dst_reg(prev_count), this->vertex_count, brw_imm_ud(0xffffffffu)));
src_reg mask(this, glsl_type::uint_type);
/* Note: we're relying on the fact that the GEN SHL instruction only pays
* attention to the lower 5 bits of its second source argument, so on this
......
This diff is collapsed.
......@@ -71,7 +71,7 @@ namespace {
bld.MOV(writemask(tmp, mask), src);
if (n < 4)
bld.MOV(writemask(tmp, ~mask), 0);
bld.MOV(writemask(tmp, ~mask), brw_imm_d(0));
return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1);
}
......@@ -143,7 +143,7 @@ namespace brw {
/* Emit the message send instruction. */
const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz);
vec4_instruction *inst =
bld.emit(op, dst, src_reg(payload), usurface, arg);
bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg));
inst->mlen = sz;
inst->regs_written = ret_sz;
inst->header_size = header_sz;
......@@ -235,7 +235,7 @@ namespace brw {
const vec4_builder ubld = bld.exec_all();
const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.MOV(dst, src_reg(0));
ubld.MOV(dst, brw_imm_d(0));
if (bld.shader->devinfo->gen == 7 &&
!bld.shader->devinfo->is_haswell) {
......@@ -243,7 +243,7 @@ namespace brw {
* have no SIMD4x2 variant. We only use the two X channels
* in that case, mask everything else out.
*/
ubld.MOV(writemask(dst, WRITEMASK_W), src_reg(0x11));
ubld.MOV(writemask(dst, WRITEMASK_W), brw_imm_d(0x11));
}
return src_reg(dst);
......
......@@ -50,7 +50,7 @@ vec4_vs_visitor::emit_prolog()
dst_reg dst = reg;
dst.type = brw_type_for_base_type(glsl_type::vec4_type);
dst.writemask = (1 << (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK)) - 1;
emit(MUL(dst, src_reg(dst), src_reg(1.0f / 65536.0f)));
emit(MUL(dst, src_reg(dst), brw_imm_f(1.0f / 65536.0f)));
}
/* Do sign recovery for 2101010 formats if required. */
......@@ -58,8 +58,8 @@ vec4_vs_visitor::emit_prolog()
if (sign_recovery_shift.file == BAD_FILE) {
/* shift constant: <22,22,22,30> */
sign_recovery_shift = dst_reg(this, glsl_type::uvec4_type);
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_XYZ), src_reg(22u)));
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_W), src_reg(30u)));
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_XYZ), brw_imm_ud(22u)));
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_W), brw_imm_ud(30u)));
}
emit(SHL(reg_ud, src_reg(reg_ud), src_reg(sign_recovery_shift)));
......@@ -87,16 +87,16 @@ vec4_vs_visitor::emit_prolog()
/* mul constant: 1 / (2^(b-1) - 1) */
es3_normalize_factor = dst_reg(this, glsl_type::vec4_type);
emit(MOV(writemask(es3_normalize_factor, WRITEMASK_XYZ),
src_reg(1.0f / ((1<<9) - 1))));
brw_imm_f(1.0f / ((1<<9) - 1))));
emit(MOV(writemask(es3_normalize_factor, WRITEMASK_W),
src_reg(1.0f / ((1<<1) - 1))));
brw_imm_f(1.0f / ((1<<1) - 1))));
}
dst_reg dst = reg;
dst.type = brw_type_for_base_type(glsl_type::vec4_type);
emit(MOV(dst, src_reg(reg_d)));
emit(MUL(dst, src_reg(dst), src_reg(es3_normalize_factor)));
emit_minmax(BRW_CONDITIONAL_GE, dst, src_reg(dst), src_reg(-1.0f));
emit_minmax(BRW_CONDITIONAL_GE, dst, src_reg(dst), brw_imm_f(-1.0f));
} else {
/* The following equations are from the OpenGL 3.2 specification:
*
......@@ -113,9 +113,9 @@ vec4_vs_visitor::emit_prolog()
/* 1 / (2^b - 1) for b=<10,10,10,2> */
normalize_factor = dst_reg(this, glsl_type::vec4_type);
emit(MOV(writemask(normalize_factor, WRITEMASK_XYZ),
src_reg(1.0f / ((1<<10) - 1))));
brw_imm_f(1.0f / ((1<<10) - 1))));
emit(MOV(writemask(normalize_factor, WRITEMASK_W),
src_reg(1.0f / ((1<<2) - 1))));
brw_imm_f(1.0f / ((1<<2) - 1))));
}
dst_reg dst = reg;
......@@ -124,8 +124,8 @@ vec4_vs_visitor::emit_prolog()
/* For signed normalization, we want the numerator to be 2c+1. */
if (wa_flags & BRW_ATTRIB_WA_SIGN) {
emit(MUL(dst, src_reg(dst), src_reg(2.0f)));
emit(ADD(dst, src_reg(dst), src_reg(1.0f)));
emit(MUL(dst, src_reg(dst), brw_imm_f(2.0f)));
emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f)));
}
emit(MUL(dst, src_reg(dst), src_reg(normalize_factor)));
......
......@@ -145,7 +145,7 @@ TEST_F(cmod_propagation_test, basic)
dst_reg dest = dst_reg(v, glsl_type::float_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
......@@ -181,7 +181,7 @@ TEST_F(cmod_propagation_test, basic_different_dst_writemask)
dst_reg dest = dst_reg(v, glsl_type::float_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
bld.ADD(dest, src0, src1);
......@@ -217,8 +217,8 @@ TEST_F(cmod_propagation_test, andz_one)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg one(1);
src_reg zero(brw_imm_f(0.0f));
src_reg one(brw_imm_d(1));
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_Z,
......@@ -253,7 +253,7 @@ TEST_F(cmod_propagation_test, non_cmod_instruction)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::uint_type);
src_reg src0 = src_reg(v, glsl_type::uint_type);
src_reg zero(0u);
src_reg zero(brw_imm_ud(0u));
bld.FBL(dest, src0);
bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
......@@ -288,7 +288,7 @@ TEST_F(cmod_propagation_test, intervening_flag_write)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest, src0, src1);
bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
......@@ -328,7 +328,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest0, src0, src1);
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, BRW_CONDITIONAL_GE);
......@@ -367,7 +367,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::vec2_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(offset(dest, 2), src0, src1);
bld.emit(SHADER_OPCODE_TEX, dest, src2)
->regs_written = 4;
......@@ -409,7 +409,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read_same_value)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
......@@ -449,7 +449,7 @@ TEST_F(cmod_propagation_test, negate)
dst_reg dest = dst_reg(v, glsl_type::float_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest, src0, src1);
src_reg tmp_src = src_reg(dest);
tmp_src.negate = true;
......@@ -521,7 +521,7 @@ TEST_F(cmod_propagation_test, different_types_cmod_with_zero)
dst_reg dest = dst_reg(v, glsl_type::int_type);
src_reg src0 = src_reg(v, glsl_type::int_type);
src_reg src1 = src_reg(v, glsl_type::int_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest, src0, src1);
bld.CMP(bld.null_reg_f(), retype(src_reg(dest), BRW_REGISTER_TYPE_F), zero,
BRW_CONDITIONAL_GE);
......@@ -555,8 +555,8 @@ TEST_F(cmod_propagation_test, andnz_non_one)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg nonone(38);
src_reg zero(brw_imm_f(0.0f));
src_reg nonone(brw_imm_d(38));
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_NZ,
......@@ -594,7 +594,7 @@ TEST_F(cmod_propagation_test, basic_vec4)
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
src_reg src0 = src_reg(v, glsl_type::vec4_type);
src_reg src1 = src_reg(v, glsl_type::vec4_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.MUL(dest, src0, src1);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_NZ);
......@@ -628,7 +628,7 @@ TEST_F(cmod_propagation_test, basic_vec4_different_dst_writemask)
dest.writemask = WRITEMASK_X;
src_reg src0 = src_reg(v, glsl_type::vec4_type);
src_reg src1 = src_reg(v, glsl_type::vec4_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
bld.MUL(dest, src0, src1);
......@@ -668,7 +668,7 @@ TEST_F(cmod_propagation_test, mad_one_component_vec4)
src_reg src2 = src_reg(v, glsl_type::vec4_type);
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
src2.negate = true;
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
src_reg tmp(dest);
tmp.swizzle = BRW_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_f();
......@@ -710,7 +710,7 @@ TEST_F(cmod_propagation_test, mad_more_one_component_vec4)
src_reg src2 = src_reg(v, glsl_type::vec4_type);
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
src2.negate = true;
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
src_reg tmp(dest);
tmp.swizzle = BRW_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_f();
......@@ -751,7 +751,7 @@ TEST_F(cmod_propagation_test, cmp_mov_vec4)
src_reg src0 = src_reg(v, glsl_type::ivec4_type);
src0.swizzle = BRW_SWIZZLE_XXXX;
src0.file = UNIFORM;
src_reg nonone = retype(src_reg(16), BRW_REGISTER_TYPE_D);
src_reg nonone = retype(brw_imm_d(16), BRW_REGISTER_TYPE_D);
src_reg mov_src = src_reg(dest);
mov_src.swizzle = BRW_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_d();
......@@ -790,7 +790,7 @@ TEST_F(cmod_propagation_test, mul_cmp_different_channels_vec4)
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
src_reg src0 = src_reg(v, glsl_type::vec4_type);
src_reg src1 = src_reg(v, glsl_type::vec4_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
src_reg cmp_src = src_reg(dest);
cmp_src.swizzle = BRW_SWIZZLE4(0,1,3,2);
......
......@@ -162,7 +162,7 @@ TEST_F(copy_propagation_test, test_swizzle_writemask)
SWIZZLE_X,
SWIZZLE_Z))));
v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), src_reg(1.0f)));
v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
vec4_instruction *test_mov =
v->MOV(c, swizzle(src_reg(b), BRW_SWIZZLE4(SWIZZLE_W,
......
......@@ -135,7 +135,7 @@ TEST_F(register_coalesce_test, test_compute_to_mrf)
m0.writemask = WRITEMASK_X;
m0.type = BRW_REGISTER_TYPE_F;
vec4_instruction *mul = v->emit(v->MUL(temp, something, src_reg(1.0f)));
vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
v->emit(v->MOV(m0, src_reg(temp)));
register_coalesce(v);
......@@ -159,7 +159,7 @@ TEST_F(register_coalesce_test, test_multiple_use)
m1.type = BRW_REGISTER_TYPE_F;
src_reg src = src_reg(temp);
vec4_instruction *mul = v->emit(v->MUL(temp, something, src_reg(1.0f)));
vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
src.swizzle = BRW_SWIZZLE_XXXX;
v->emit(v->MOV(m0, src));
src.swizzle = BRW_SWIZZLE_XYZW;
......
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