Commit f6075096 authored by Matt Turner's avatar Matt Turner
Browse files

i965/vec4/tcs: Set conditional mod on TCS_OPCODE_SRC0_010_IS_ZERO.



Missing this causes an assertion failure in the scheduler with the next
patch.

Additionally, this gives cmod propagation enough information to optimize
code better.

total instructions in shared programs: 7112991 -> 7112852 (-0.00%)
instructions in affected programs: 25704 -> 25565 (-0.54%)
helped: 139

total cycles in shared programs: 64812898 -> 64810674 (-0.00%)
cycles in affected programs: 127224 -> 125000 (-1.75%)
helped: 139
Acked-by: Francisco Jerez's avatarFrancisco Jerez <currojerez@riseup.net>
parent 436bdd74
......@@ -1931,7 +1931,6 @@ generate_code(struct brw_codegen *p,
case TCS_OPCODE_SRC0_010_IS_ZERO:
/* If src_reg had stride like fs_reg, we wouldn't need this. */
brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
brw_inst_set_cond_modifier(devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
break;
case TCS_OPCODE_RELEASE_INPUT:
......
......@@ -184,7 +184,9 @@ vec4_tcs_visitor::emit_thread_end()
* we don't have stride in the vec4 world, nor UV immediates in
* align16, so we need an opcode to get invocation_id<0,4,0>.
*/
emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), invocation_id);
set_condmod(BRW_CONDITIONAL_Z,
emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
invocation_id));
emit(IF(BRW_PREDICATE_NORMAL));
for (unsigned i = 0; i < key->input_vertices; i += 2) {
/* If we have an odd number of input vertices, the last will be
......
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