Commit 26391cce authored by Ian Romanick's avatar Ian Romanick

intel/compiler: Lower ffma on Gen4 and Gen5

flrp32 is also a 3-source instruction, but there is another pending
series that handles that for Gen4 and Gen5.

v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen
Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <>
Reviewed-by: Matt Turner's avatarMatt Turner <>
parent fd1fa9af
......@@ -183,6 +183,10 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
nir_options->lower_flrp32 = true;
/* Prior to Gen6, there are no three source operations. */
nir_options->lower_ffma = devinfo->gen < 6;
nir_options->lower_int64_options = int64_options;
nir_options->lower_doubles_options = fp64_options;
compiler->glsl_compiler_options[i].NirOptions = nir_options;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment