ir3_compiler_nir.c 108 KB
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/*
 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Rob Clark <robclark@freedesktop.org>
 */

#include <stdarg.h>

#include "util/u_string.h"
#include "util/u_memory.h"
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#include "util/u_math.h"
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#include "ir3_compiler.h"
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#include "ir3_image.h"
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#include "ir3_shader.h"
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#include "ir3_nir.h"
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#include "instr-a3xx.h"
#include "ir3.h"
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#include "ir3_context.h"
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static struct ir3_instruction *
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create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
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		struct ir3_instruction *address, struct ir3_instruction *collect)
{
	struct ir3_block *block = ctx->block;
	struct ir3_instruction *mov;
	struct ir3_register *src;

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	mov = ir3_instr_create(block, OPC_MOV);
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	mov->cat1.src_type = TYPE_U32;
	mov->cat1.dst_type = TYPE_U32;
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	__ssa_dst(mov);
	src = __ssa_src(mov, collect, IR3_REG_RELATIV);
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	src->size  = arrsz;
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	src->array.offset = n;
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	ir3_instr_set_address(mov, address);
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	return mov;
}

static struct ir3_instruction *
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create_input(struct ir3_context *ctx, unsigned compmask)
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{
	struct ir3_instruction *in;

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	in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
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	in->input.sysval = ~0;
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	__ssa_dst(in)->wrmask = compmask;
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	array_insert(ctx->ir, ctx->ir->inputs, in);
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	return in;
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}

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static struct ir3_instruction *
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create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
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{
	struct ir3_block *block = ctx->block;
	struct ir3_instruction *instr;
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	/* packed inloc is fixed up later: */
	struct ir3_instruction *inloc = create_immed(block, n);
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	if (use_ldlv) {
		instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
		instr->cat6.type = TYPE_U32;
		instr->cat6.iim_val = 1;
	} else {
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		instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
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		instr->regs[2]->wrmask = 0x3;
	}

	return instr;
}

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static struct ir3_instruction *
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create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
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{
	/* first four vec4 sysval's reserved for UBOs: */
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	/* NOTE: dp is in scalar, but there can be >4 dp components: */
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	struct ir3_const_state *const_state = &ctx->so->shader->const_state;
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	unsigned n = const_state->offsets.driver_param;
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	unsigned r = regid(n + dp / 4, dp % 4);
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	return create_uniform(ctx->block, r);
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}

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/*
 * Adreno uses uint rather than having dedicated bool type,
 * which (potentially) requires some conversion, in particular
 * when using output of an bool instr to int input, or visa
 * versa.
 *
 *         | Adreno  |  NIR  |
 *  -------+---------+-------+-
 *   true  |    1    |  ~0   |
 *   false |    0    |   0   |
 *
 * To convert from an adreno bool (uint) to nir, use:
 *
 *    absneg.s dst, (neg)src
 *
 * To convert back in the other direction:
 *
 *    absneg.s dst, (abs)arc
 *
 * The CP step can clean up the absneg.s that cancel each other
 * out, and with a slight bit of extra cleverness (to recognize
 * the instructions which produce either a 0 or 1) can eliminate
 * the absneg.s's completely when an instruction that wants
 * 0/1 consumes the result.  For example, when a nir 'bcsel'
 * consumes the result of 'feq'.  So we should be able to get by
 * without a boolean resolve step, and without incuring any
 * extra penalty in instruction count.
 */

/* NIR bool -> native (adreno): */
static struct ir3_instruction *
ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
{
	return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
}

/* native (adreno) -> NIR bool: */
static struct ir3_instruction *
ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
{
	return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
}

/*
 * alu/sfu instructions:
 */

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static struct ir3_instruction *
create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
		unsigned src_bitsize, nir_op op)
{
	type_t src_type, dst_type;

	switch (op) {
	case nir_op_f2f32:
	case nir_op_f2f16_rtne:
	case nir_op_f2f16_rtz:
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	case nir_op_f2f16:
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	case nir_op_f2i32:
	case nir_op_f2i16:
	case nir_op_f2i8:
	case nir_op_f2u32:
	case nir_op_f2u16:
	case nir_op_f2u8:
		switch (src_bitsize) {
		case 32:
			src_type = TYPE_F32;
			break;
		case 16:
			src_type = TYPE_F16;
			break;
		default:
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			ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
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		}
		break;

	case nir_op_i2f32:
	case nir_op_i2f16:
	case nir_op_i2i32:
	case nir_op_i2i16:
	case nir_op_i2i8:
		switch (src_bitsize) {
		case 32:
			src_type = TYPE_S32;
			break;
		case 16:
			src_type = TYPE_S16;
			break;
		case 8:
			src_type = TYPE_S8;
			break;
		default:
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			ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
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		}
		break;

	case nir_op_u2f32:
	case nir_op_u2f16:
	case nir_op_u2u32:
	case nir_op_u2u16:
	case nir_op_u2u8:
		switch (src_bitsize) {
		case 32:
			src_type = TYPE_U32;
			break;
		case 16:
			src_type = TYPE_U16;
			break;
		case 8:
			src_type = TYPE_U8;
			break;
		default:
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			ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
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		}
		break;

	default:
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		ir3_context_error(ctx, "invalid conversion op: %u", op);
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	}

	switch (op) {
	case nir_op_f2f32:
	case nir_op_i2f32:
	case nir_op_u2f32:
		dst_type = TYPE_F32;
		break;

	case nir_op_f2f16_rtne:
	case nir_op_f2f16_rtz:
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	case nir_op_f2f16:
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		/* TODO how to handle rounding mode? */
	case nir_op_i2f16:
	case nir_op_u2f16:
		dst_type = TYPE_F16;
		break;

	case nir_op_f2i32:
	case nir_op_i2i32:
		dst_type = TYPE_S32;
		break;

	case nir_op_f2i16:
	case nir_op_i2i16:
		dst_type = TYPE_S16;
		break;

	case nir_op_f2i8:
	case nir_op_i2i8:
		dst_type = TYPE_S8;
		break;

	case nir_op_f2u32:
	case nir_op_u2u32:
		dst_type = TYPE_U32;
		break;

	case nir_op_f2u16:
	case nir_op_u2u16:
		dst_type = TYPE_U16;
		break;

	case nir_op_f2u8:
	case nir_op_u2u8:
		dst_type = TYPE_U8;
		break;

	default:
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		ir3_context_error(ctx, "invalid conversion op: %u", op);
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	}

	return ir3_COV(ctx->block, src, src_type, dst_type);
}

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static void
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emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
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{
	const nir_op_info *info = &nir_op_infos[alu->op];
	struct ir3_instruction **dst, *src[info->num_inputs];
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	unsigned bs[info->num_inputs];     /* bit size */
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	struct ir3_block *b = ctx->block;
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	unsigned dst_sz, wrmask;
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	type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
			TYPE_U16 : TYPE_U32;
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	if (alu->dest.dest.is_ssa) {
		dst_sz = alu->dest.dest.ssa.num_components;
		wrmask = (1 << dst_sz) - 1;
	} else {
		dst_sz = alu->dest.dest.reg.reg->num_components;
		wrmask = alu->dest.write_mask;
	}

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	dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
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	/* Vectors are special in that they have non-scalarized writemasks,
	 * and just take the first swizzle channel for each argument in
	 * order into each writemask channel.
	 */
	if ((alu->op == nir_op_vec2) ||
			(alu->op == nir_op_vec3) ||
			(alu->op == nir_op_vec4)) {

		for (int i = 0; i < info->num_inputs; i++) {
			nir_alu_src *asrc = &alu->src[i];

			compile_assert(ctx, !asrc->abs);
			compile_assert(ctx, !asrc->negate);

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			src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
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			if (!src[i])
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				src[i] = create_immed_typed(ctx->block, 0, dst_type);
			dst[i] = ir3_MOV(b, src[i], dst_type);
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		}

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		ir3_put_dst(ctx, &alu->dest.dest);
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		return;
	}

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	/* We also get mov's with more than one component for mov's so
	 * handle those specially:
	 */
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	if (alu->op == nir_op_mov) {
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		nir_alu_src *asrc = &alu->src[0];
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		struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
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		for (unsigned i = 0; i < dst_sz; i++) {
			if (wrmask & (1 << i)) {
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				dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
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			} else {
				dst[i] = NULL;
			}
		}

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		ir3_put_dst(ctx, &alu->dest.dest);
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		return;
	}

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	/* General case: We can just grab the one used channel per src. */
	for (int i = 0; i < info->num_inputs; i++) {
		unsigned chan = ffs(alu->dest.write_mask) - 1;
		nir_alu_src *asrc = &alu->src[i];

		compile_assert(ctx, !asrc->abs);
		compile_assert(ctx, !asrc->negate);

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		src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
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		bs[i] = nir_src_bit_size(asrc->src);
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		compile_assert(ctx, src[i]);
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	}

	switch (alu->op) {
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	case nir_op_f2f32:
	case nir_op_f2f16_rtne:
	case nir_op_f2f16_rtz:
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	case nir_op_f2f16:
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	case nir_op_f2i32:
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	case nir_op_f2i16:
	case nir_op_f2i8:
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	case nir_op_f2u32:
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	case nir_op_f2u16:
	case nir_op_f2u8:
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	case nir_op_i2f32:
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	case nir_op_i2f16:
	case nir_op_i2i32:
	case nir_op_i2i16:
	case nir_op_i2i8:
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	case nir_op_u2f32:
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	case nir_op_u2f16:
	case nir_op_u2u32:
	case nir_op_u2u16:
	case nir_op_u2u8:
		dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
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		break;
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	case nir_op_fquantize2f16:
		dst[0] = create_cov(ctx,
							create_cov(ctx, src[0], 32, nir_op_f2f16),
							16, nir_op_f2f32);
		break;
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	case nir_op_f2b16: {
		struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
		dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
		dst[0]->cat2.condition = IR3_COND_NE;
		break;
	}
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	case nir_op_f2b32:
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		dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
		dst[0]->cat2.condition = IR3_COND_NE;
		break;
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	case nir_op_b2f16:
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		dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
		break;
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	case nir_op_b2f32:
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		dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
		break;
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	case nir_op_b2i8:
	case nir_op_b2i16:
	case nir_op_b2i32:
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		dst[0] = ir3_b2n(b, src[0]);
		break;
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	case nir_op_i2b16: {
		struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
		dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
		dst[0]->cat2.condition = IR3_COND_NE;
		break;
	}
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	case nir_op_i2b32:
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		dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
		dst[0]->cat2.condition = IR3_COND_NE;
		break;

	case nir_op_fneg:
		dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
		break;
	case nir_op_fabs:
		dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
		break;
	case nir_op_fmax:
		dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
		break;
	case nir_op_fmin:
		dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_fsat:
		/* if there is just a single use of the src, and it supports
		 * (sat) bit, we can just fold the (sat) flag back to the
		 * src instruction and create a mov.  This is easier for cp
		 * to eliminate.
		 *
		 * TODO probably opc_cat==4 is ok too
		 */
		if (alu->src[0].src.is_ssa &&
				(list_length(&alu->src[0].src.ssa->uses) == 1) &&
				((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
			src[0]->flags |= IR3_INSTR_SAT;
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			dst[0] = ir3_MOV(b, src[0], dst_type);
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		} else {
			/* otherwise generate a max.f that saturates.. blob does
			 * similar (generating a cat2 mov using max.f)
			 */
			dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
			dst[0]->flags |= IR3_INSTR_SAT;
		}
		break;
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	case nir_op_fmul:
		dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
		break;
	case nir_op_fadd:
		dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
		break;
	case nir_op_fsub:
		dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
		break;
	case nir_op_ffma:
		dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
		break;
	case nir_op_fddx:
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	case nir_op_fddx_coarse:
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		dst[0] = ir3_DSX(b, src[0], 0);
		dst[0]->cat5.type = TYPE_F32;
		break;
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	case nir_op_fddx_fine:
		dst[0] = ir3_DSXPP_1(b, src[0], 0);
		dst[0]->cat5.type = TYPE_F32;
		break;
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	case nir_op_fddy:
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	case nir_op_fddy_coarse:
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		dst[0] = ir3_DSY(b, src[0], 0);
		dst[0]->cat5.type = TYPE_F32;
		break;
		break;
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	case nir_op_fddy_fine:
		dst[0] = ir3_DSYPP_1(b, src[0], 0);
		dst[0]->cat5.type = TYPE_F32;
		break;
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	case nir_op_flt16:
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	case nir_op_flt32:
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		dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_LT;
		break;
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	case nir_op_fge16:
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	case nir_op_fge32:
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		dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_GE;
		break;
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	case nir_op_feq16:
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	case nir_op_feq32:
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		dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_EQ;
		break;
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	case nir_op_fne16:
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	case nir_op_fne32:
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		dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_NE;
		break;
	case nir_op_fceil:
		dst[0] = ir3_CEIL_F(b, src[0], 0);
		break;
	case nir_op_ffloor:
		dst[0] = ir3_FLOOR_F(b, src[0], 0);
		break;
	case nir_op_ftrunc:
		dst[0] = ir3_TRUNC_F(b, src[0], 0);
		break;
	case nir_op_fround_even:
		dst[0] = ir3_RNDNE_F(b, src[0], 0);
		break;
	case nir_op_fsign:
		dst[0] = ir3_SIGN_F(b, src[0], 0);
		break;

	case nir_op_fsin:
		dst[0] = ir3_SIN(b, src[0], 0);
		break;
	case nir_op_fcos:
		dst[0] = ir3_COS(b, src[0], 0);
		break;
	case nir_op_frsq:
		dst[0] = ir3_RSQ(b, src[0], 0);
		break;
	case nir_op_frcp:
		dst[0] = ir3_RCP(b, src[0], 0);
		break;
	case nir_op_flog2:
		dst[0] = ir3_LOG2(b, src[0], 0);
		break;
	case nir_op_fexp2:
		dst[0] = ir3_EXP2(b, src[0], 0);
		break;
	case nir_op_fsqrt:
		dst[0] = ir3_SQRT(b, src[0], 0);
		break;

	case nir_op_iabs:
		dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
		break;
	case nir_op_iadd:
		dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
		break;
	case nir_op_iand:
		dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
		break;
	case nir_op_imax:
		dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_umax:
		dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_imin:
		dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_umin:
		dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_umul_low:
		dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
		break;
	case nir_op_imadsh_mix16:
		dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
		break;
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	case nir_op_imad24_ir3:
		dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
		break;
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	case nir_op_imul24:
		dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_ineg:
		dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
		break;
	case nir_op_inot:
		dst[0] = ir3_NOT_B(b, src[0], 0);
		break;
	case nir_op_ior:
		dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
		break;
	case nir_op_ishl:
		dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
		break;
	case nir_op_ishr:
		dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
		break;
	case nir_op_isub:
		dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
		break;
	case nir_op_ixor:
		dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
		break;
	case nir_op_ushr:
		dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
		break;
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	case nir_op_ilt16:
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	case nir_op_ilt32:
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		dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_LT;
		break;
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	case nir_op_ige16:
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	case nir_op_ige32:
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		dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_GE;
		break;
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	case nir_op_ieq16:
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	case nir_op_ieq32:
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		dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_EQ;
		break;
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	case nir_op_ine16:
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	case nir_op_ine32:
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		dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_NE;
		break;
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	case nir_op_ult16:
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	case nir_op_ult32:
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		dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_LT;
		break;
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	case nir_op_uge16:
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	case nir_op_uge32:
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		dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
		dst[0]->cat2.condition = IR3_COND_GE;
		break;

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	case nir_op_b16csel:
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	case nir_op_b32csel: {
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		struct ir3_instruction *cond = src[0];
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		/* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
		 * we can ignore that and use original cond, since the nonzero-ness of
		 * cond stays the same.
		 */
		if (cond->opc == OPC_ABSNEG_S &&
				cond->flags == 0 &&
				(cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
			cond = cond->regs[1]->instr;
		}
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		compile_assert(ctx, bs[1] == bs[2]);
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		if (bs[1] != bs[0]) {
			struct hash_entry *prev_entry =
				_mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
			if (prev_entry) {
				cond = prev_entry->data;
			} else {
				/* Make sure the boolean condition has the same bit size as the other
				 * two arguments, adding a conversion if necessary.
				 */
				if (bs[1] < bs[0])
					cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
				else if (bs[1] > bs[0])
					cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
				_mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
			}
		}
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		if (bs[1] > 16)
			dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
		else
			dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
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		break;
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	}
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	case nir_op_bit_count: {
		// TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
		// double check on earlier gen's.  Once half-precision support is
		// in place, this should probably move to a NIR lowering pass:
		struct ir3_instruction *hi, *lo;

		hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
				TYPE_U32, TYPE_U16);
		lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);

		hi = ir3_CBITS_B(b, hi, 0);
		lo = ir3_CBITS_B(b, lo, 0);

		// TODO maybe the builders should default to making dst half-precision
		// if the src's were half precision, to make this less awkward.. otoh
		// we should probably just do this lowering in NIR.
		hi->regs[0]->flags |= IR3_REG_HALF;
		lo->regs[0]->flags |= IR3_REG_HALF;

		dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
		dst[0]->regs[0]->flags |= IR3_REG_HALF;
		dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
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		break;
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	}
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	case nir_op_ifind_msb: {
		struct ir3_instruction *cmp;
		dst[0] = ir3_CLZ_S(b, src[0], 0);
		cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
		cmp->cat2.condition = IR3_COND_GE;
		dst[0] = ir3_SEL_B32(b,
				ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
				cmp, 0, dst[0], 0);
		break;
	}
	case nir_op_ufind_msb:
		dst[0] = ir3_CLZ_B(b, src[0], 0);
		dst[0] = ir3_SEL_B32(b,
				ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
				src[0], 0, dst[0], 0);
		break;
	case nir_op_find_lsb:
		dst[0] = ir3_BFREV_B(b, src[0], 0);
		dst[0] = ir3_CLZ_B(b, dst[0], 0);
		break;
	case nir_op_bitfield_reverse:
		dst[0] = ir3_BFREV_B(b, src[0], 0);
		break;

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	default:
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		ir3_context_error(ctx, "Unhandled ALU op: %s\n",
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				nir_op_infos[alu->op].name);
		break;
	}
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	if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
		assert(dst_sz == 1);
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		if (nir_dest_bit_size(alu->dest.dest) < 32)
			dst[0]->regs[0]->flags |= IR3_REG_HALF;

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		dst[0] = ir3_n2b(b, dst[0]);
	}

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	if (nir_dest_bit_size(alu->dest.dest) < 32) {
		for (unsigned i = 0; i < dst_sz; i++) {
			dst[i]->regs[0]->flags |= IR3_REG_HALF;
		}
	}

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	ir3_put_dst(ctx, &alu->dest.dest);
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}

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static void
emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
							struct ir3_instruction **dst)
{
	struct ir3_block *b = ctx->block;

	unsigned ncomp = intr->num_components;
	struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
	struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
	struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
	ldc->regs[0]->wrmask = MASK(ncomp);
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	ldc->cat6.iim_val = ncomp;
	ldc->cat6.d = nir_intrinsic_base(intr);
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	ldc->cat6.type = TYPE_U32;

	nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
	if (bindless) {
		ldc->flags |= IR3_INSTR_B;
		ldc->cat6.base = nir_intrinsic_desc_set(bindless);
		ctx->so->bindless_ubo = true;
	}

	ir3_split_dest(b, dst, ldc, 0, ncomp);
}


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/* handles direct/indirect UBO reads: */
static void
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emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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		struct ir3_instruction **dst)
{
	struct ir3_block *b = ctx->block;
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	struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
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	struct ir3_const_state *const_state = &ctx->so->shader->const_state;
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	unsigned ubo = regid(const_state->offsets.ubo, 0);
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	const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
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	int off = 0;
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	/* First src is ubo index, which could either be an immed or not: */
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	src0 = ir3_get_src(ctx, &intr->src[0])[0];
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	if (is_same_type_mov(src0) &&
			(src0->regs[1]->flags & IR3_REG_IMMED)) {
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		base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
		base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
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	} else {
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		base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
		base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
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		/* NOTE: since relative addressing is used, make sure constlen is
		 * at least big enough to cover all the UBO addresses, since the
		 * assembler won't know what the max address reg is.
		 */
		ctx->so->constlen = MAX2(ctx->so->constlen,
			const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
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	}

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	/* note: on 32bit gpu's base_hi is ignored and DCE'd */
	addr = base_lo;

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	if (nir_src_is_const(intr->src[1])) {
		off += nir_src_as_uint(intr->src[1]);
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	} else {
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		/* For load_ubo_indirect, second src is indirect offset: */
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		src1 = ir3_get_src(ctx, &intr->src[1])[0];
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		/* and add offset to addr: */
		addr = ir3_ADD_S(b, addr, 0, src1, 0);
	}

	/* if offset is to large to encode in the ldg, split it out: */
	if ((off + (intr->num_components * 4)) > 1024) {
		/* split out the minimal amount to improve the odds that
		 * cp can fit the immediate in the add.s instruction:
		 */
		unsigned off2 = off + (intr->num_components * 4) - 1024;
		addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
		off -= off2;
	}

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	if (ptrsz == 2) {
		struct ir3_instruction *carry;

		/* handle 32b rollover, ie:
		 *   if (addr < base_lo)
		 *      base_hi++
		 */
		carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
		carry->cat2.condition = IR3_COND_LT;
		base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);

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		addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
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	}

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	for (int i = 0; i < intr->num_components; i++) {
		struct ir3_instruction *load =
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			ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
					create_immed(b, off + i * 4), 0);
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		load->cat6.type = TYPE_U32;
		dst[i] = load;
	}
}

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/* src[] = { block_index } */
static void
emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
		struct ir3_instruction **dst)
{
	/* SSBO size stored as a const starting at ssbo_sizes: */
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	struct ir3_const_state *const_state = &ctx->so->shader->const_state;
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	unsigned blk_idx = nir_src_as_uint(intr->src[0]);
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	unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
		const_state->ssbo_size.off[blk_idx];
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	debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
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	dst[0] = create_uniform(ctx->block, idx);
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}

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/* src[] = { offset }. const_index[] = { base } */
static void
emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
		struct ir3_instruction **dst)
{
	struct ir3_block *b = ctx->block;
	struct ir3_instruction *ldl, *offset;
	unsigned base;

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	offset = ir3_get_src(ctx, &intr->src[0])[0];
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	base   = nir_intrinsic_base(intr);
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	ldl = ir3_LDL(b, offset, 0,
			create_immed(b, intr->num_components), 0,
			create_immed(b, base), 0);

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	ldl->cat6.type = utype_dst(intr->dest);
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	ldl->regs[0]->wrmask = MASK(intr->num_components);

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	ldl->barrier_class = IR3_BARRIER_SHARED_R;
	ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
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	ir3_split_dest(b, dst, ldl, 0, intr->num_components);
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}

/* src[] = { value, offset }. const_index[] = { base, write_mask } */
static void
emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
{
	struct ir3_block *b = ctx->block;
	struct ir3_instruction *stl, *offset;
	struct ir3_instruction * const *value;
	unsigned base, wrmask;

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	value  = ir3_get_src(ctx, &intr->src[0]);
	offset = ir3_get_src(ctx, &intr->src[1])[0];
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	base   = nir_intrinsic_base(intr);
	wrmask = nir_intrinsic_write_mask(intr);
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	/* Combine groups of consecutive enabled channels in one write
	 * message. We use ffs to find the first enabled channel and then ffs on
	 * the bit-inverse, down-shifted writemask to determine the length of
	 * the block of enabled bits.
	 *
	 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
	 */
	while (wrmask) {
		unsigned first_component = ffs(wrmask) - 1;
		unsigned length = ffs(~(wrmask >> first_component)) - 1;

		stl = ir3_STL(b, offset, 0,
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			ir3_create_collect(ctx, &value[first_component], length), 0,
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			create_immed(b, length), 0);
		stl->cat6.dst_offset = first_component + base;
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		stl->cat6.type = utype_src(intr->src[0]);
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		stl->barrier_class = IR3_BARRIER_SHARED_W;
		stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
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		array_insert(b, b->keeps, stl);

		/* Clear the bits in the writemask that we just wrote, then try
		 * again to see if more channels are left.
		 */
		wrmask &= (15 << (first_component + length));
	}
}

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/* src[] = { offset }. const_index[] = { base } */
static void
emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
		struct ir3_instruction **dst)
{
	struct ir3_block *b = ctx->block;
	struct ir3_instruction *load, *offset;
	unsigned base;

	offset = ir3_get_src(ctx, &intr->src[0])[0];
	base   = nir_intrinsic_base(intr);

	load = ir3_LDLW(b, offset, 0,
			create_immed(b, intr->num_components), 0,
			create_immed(b, base), 0);

	load->cat6.type = utype_dst(intr->dest);
	load->regs[0]->wrmask = MASK(intr->num_components);

	load->barrier_class = IR3_BARRIER_SHARED_R;
	load->barrier_conflict = IR3_BARRIER_SHARED_W;

	ir3_split_dest(b, dst, load, 0, intr->num_components);
}

/* src[] = { value, offset }. const_index[] = { base, write_mask } */
static void
emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
{
	struct ir3_block *b = ctx->block;
	struct ir3_instruction *store, *offset;
	struct ir3_instruction * const *value;
	unsigned base, wrmask;

	value  = ir3_get_src(ctx, &intr->src[0]);
	offset = ir3_get_src(ctx, &intr->src[1])[0];

	base   = nir_intrinsic_base(intr);
	wrmask = nir_intrinsic_write_mask(intr);

	/* Combine groups of consecutive enabled channels in one write
	 * message. We use ffs to find the first enabled channel and then ffs on
	 * the bit-inverse, down-shifted writemask to determine the length of
	 * the block of enabled bits.
	 *
	 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
	 */
	while (wrmask) {
		unsigned first_component = ffs(wrmask) - 1;
		unsigned length = ffs(~(wrmask >> first_component)) - 1;

		store = ir3_STLW(b, offset, 0,
			ir3_create_collect(ctx, &value[first_component], length), 0,
			create_immed(b, length), 0);

		store->cat6.dst_offset = first_component + base;
		store->cat6.type = utype_src(intr->src[0]);
		store->barrier_class = IR3_BARRIER_SHARED_W;
		store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;

		array_insert(b, b->keeps, store);

		/* Clear the bits in the writemask that we just wrote, then try
		 * again to see if more channels are left.
		 */
		wrmask &= (15 << (first_component + length));
	}
}

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/*
 * CS shared variable atomic intrinsics
 *
 * All of the shared variable atomic memory operations read a value from
 * memory, compute a new value using one of the operations below, write the
 * new value to memory, and return the original value read.
 *
 * All operations take 2 sources except CompSwap that takes 3. These
 * sources represent:
 *
 * 0: The offset into the shared variable storage region that the atomic
 *    operation will operate on.
 * 1: The data parameter to the atomic function (i.e. the value to add
 *    in shared_atomic_add, etc).
 * 2: For CompSwap only: the second data parameter.
 */
static struct ir3_instruction *
emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
{
	struct ir3_block *b = ctx->block;
	struct ir3_instruction *atomic, *src0, *src1;
	type_t type = TYPE_U32;

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	src0 = ir3_get_src(ctx, &intr->src[0])[0];   /* offset */
	src1 = ir3_get_src(ctx, &intr->src[1])[0];   /* value */
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	switch (intr->intrinsic) {
	case nir_intrinsic_shared_atomic_add:
		atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_imin:
		atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
		type = TYPE_S32;
		break;
	case nir_intrinsic_shared_atomic_umin:
		atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_imax:
		atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
		type = TYPE_S32;
		break;
	case nir_intrinsic_shared_atomic_umax:
		atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_and:
		atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_or:
		atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_xor:
		atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_exchange:
		atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
		break;
	case nir_intrinsic_shared_atomic_comp_swap:
		/* for cmpxchg, src1 is [ui]vec2(data, compare): */
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		src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
			ir3_get_src(ctx, &intr->src[2])[0],
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			src1,
		}, 2);
		atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
		break;
	default:
		unreachable("boo");
	}

	atomic->cat6.iim_val = 1;
	atomic->cat6.d = 1;
	atomic->cat6.type = type;
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	atomic->barrier_class = IR3_BARRIER_SHARED_W;
	atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
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	/* even if nothing consume the result, we can't DCE the instruction: */
	array_insert(b, b->keeps, atomic);

	return atomic;
}

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struct tex_src_info {
	/* For prefetch */
	unsigned tex_base, samp_base, tex_idx, samp_idx;
	/* For normal tex instructions */
	unsigned base, combined_idx, a1_val, flags;
	struct ir3_instruction *samp_tex;
};

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/* TODO handle actual indirect/dynamic case.. which is going to be weird
 * to handle with the image_mapping table..
 */
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static struct tex_src_info
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get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
{
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	struct ir3_block *b = ctx->block;
	struct tex_src_info info = { 0 };
	nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
	ctx->so->bindless_tex = true;
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	if (bindless_tex) {
		/* Bindless case */
		info.flags |= IR3_INSTR_B;
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		/* Gather information required to determine which encoding to
		 * choose as well as for prefetch.
		 */
		info.tex_base = nir_intrinsic_desc_set(bindless_tex);
		bool tex_const = nir_src_is_const(bindless_tex->src[0]);
		if (tex_const)
			info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
		info.samp_idx = 0;

		/* Choose encoding. */
		if (tex_const && info.tex_idx < 256) {
			if (info.tex_idx < 16) {
				/* Everything fits within the instruction */
				info.base = info.tex_base;
				info.combined_idx = info.samp_idx | (info.tex_idx << 4);
			} else {
				info.base = info.tex_base;
				info.a1_val = info.tex_idx << 3;
				info.combined_idx = 0;
				info.flags |= IR3_INSTR_A1EN;
			}
			info.samp_tex = NULL;
		} else {
			info.flags |= IR3_INSTR_S2EN;
			info.base = info.tex_base;

			/* Note: the indirect source is now a vec2 instead of hvec2 */
			struct ir3_instruction *texture, *sampler;

			texture = ir3_get_src(ctx, &intr->src[0])[0];
			sampler = create_immed(b, 0);
			info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
				texture,
				sampler,
			}, 2);
		}
	} else {
		info.flags |= IR3_INSTR_S2EN;
		unsigned slot = nir_src_as_uint(intr->src[0]);
		unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
		struct ir3_instruction *texture, *sampler;

		texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
		sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);

		info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
			sampler,
			texture,
		}, 2);
	}
	
	return info;
}

static struct ir3_instruction *
emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
		 type_t type, unsigned wrmask, struct ir3_instruction *src0,
		 struct ir3_instruction *src1)
{
	struct ir3_instruction *sam, *addr;
	if (info.flags & IR3_INSTR_A1EN) {
		addr = ir3_get_addr1(ctx, info.a1_val);
	}
	sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
			info.samp_tex, src0, src1);
	if (info.flags & IR3_INSTR_A1EN) {
		ir3_instr_set_address(sam, addr);
	}
	if (info.flags & IR3_INSTR_B) {
		sam->cat5.tex_base = info.base;
		sam->cat5.samp = info.combined_idx;
	}
	return sam;
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}

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/* src[] = { deref, coord, sample_index }. const_index[] = {} */
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static void
emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
		struct ir3_instruction **dst)
{
	struct ir3_block *b = ctx->block;
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	struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
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	struct ir3_instruction *sam;