Commit 0d8c5733 authored by Karol Herbst's avatar Karol Herbst 🐧
Browse files

nvc0: only allocate 2 registers less for gv100+

It is unclear to my why we have a +5 in there, but there is something funky
going on and we need to allocate more. On my TU17 +3 works without issues
as well though and it gives a slight performance improvement in
heavier benchmarks.
Signed-off-by: Karol Herbst's avatarKarol Herbst <>
parent c1476044
Pipeline #185257 waiting for manual action with stages
......@@ -646,7 +646,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
prog->relocs = info->bin.relocData;
prog->fixups = info->bin.fixupData;
if (info->target >= NVISA_GV100_CHIPSET)
prog->num_gprs = MIN2(info->bin.maxGPR + 5, 256); //XXX: why?
prog->num_gprs = MIN2(info->bin.maxGPR + 3, 256); //XXX: why?
prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
prog->cp.smem_size = info->bin.smemSize;
......@@ -716,7 +716,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
pipe_debug_message(debug, SHADER_INFO,
"type: %d, local: %d, shared: %d, gpr: %d, inst: %d, bytes: %d",
prog->type, info->bin.tlsSpace, info->bin.smemSize,
prog->num_gprs, info->bin.instructions,
info->bin.maxGPR + 1, info->bin.instructions,
#ifndef NDEBUG
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