- Oct 08, 2020
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Faith Ekstrand authored
It assumes the parent is a vector or scalar so we need to fail if it isn't. Fixes: 9190f82d "nir/opt_deref: Add an optimization for bitcasts" Reviewed-by: Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!7064>
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Faith Ekstrand authored
Reviewed-by: Karol Herbst <kherbst@redhat.com> Part-of: <mesa/mesa!7068>
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Andrii Simiklit authored
It fixes coverity issue: CID 1467703: (RESOURCE_LEAK): `Variable "cp" going out of scope leaks the storage it points to.` Fixes: 23c3eb1f ("driconf: Delete disjoint range support") Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7021>
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Samuel Pitoiset authored
64-bit IO are lowered with NIR. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!7008>
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Samuel Pitoiset authored
To match ACO. fossilds-db (Navi10): Totals from 20869 (15.30% of 136420) affected shaders: SGPRs: 1851128 -> 1851920 (+0.04%); split: -0.41%, +0.46% VGPRs: 1607360 -> 1608212 (+0.05%); split: -0.20%, +0.25% SpillSGPRs: 267331 -> 261350 (-2.24%); split: -3.67%, +1.43% CodeSize: 155460104 -> 155303508 (-0.10%); split: -0.21%, +0.11% MaxWaves: 179156 -> 178928 (-0.13%); split: +0.48%, -0.60% Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!6932>
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Samuel Pitoiset authored
With fmed3 if available, otherwise fallback to fmin/fmax. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!6932>
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Tomeu Vizoso authored
To get more consistent performance and results, use the performance devfreq governor and disable PM runtime. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!7011>
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Tomeu Vizoso authored
For testing Panfrost on Bifrost GPUs, add a job for dEQP GLES2 testing. Right now almost all tests are skipped, but as we make progress and things show stable, we'll be running more and more tests. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!7011>
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Tomeu Vizoso authored
Update to v5.9-rc5-based drm-misc-for-next, so we can run jobs on machines with Bifrost GPUs. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!7011>
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Kristian Høgsberg authored
This makes freedreno advertise support for PIPE_FORMAT_R8_G8B8_420_UNORM on a6xx, which enables lowering NV12 to this format. Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6693>
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Kristian Høgsberg authored
Add resource pointers ptr1 and ptr2 and offsets offset1 and offset2, and just emit relocs if the pointers are non-NULL. This lets us move a little more logic to the CSO building. Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6693>
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Kristian Høgsberg authored
Some GPUs can sample biplanar formats like NV12 natively, returning the YUV values. Add a lowering type that uses that for sampling and relies on existing colorspace conversions. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6693>
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Kristian Høgsberg authored
This is a planar, subsampled format. It's basically NV12, but without colorspace conversion. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!6693>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
On Gen7, the data cache is pretty terrible so we'd rather avoid it there. On Gen8+, it should be fine and is less likely to conflict with texturing so we should get less cache thrashing there. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!3932>
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Lionel Landwerlin authored
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <mesa/mesa!7049>
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Faith Ekstrand authored
It's identical to nir_intrinsic_load_global except that it works on data that's guaranteed to be constant throughout the shader invocation. Fixes: ff2f44d8 "intel/fs: Implement nir_intrinsic_load_global_constant" Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!6872>
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Faith Ekstrand authored
In 53bfcdee, we added load/store_scratch instructions which deviate a little bit from most memory load/store instructions in that we can't use the normal untyped read/write instructions which can read and write up to a vec4 at a time. Instead, we have to use the DWORD scattered read/write instructions which are scalar. To handle this, we added code to brw_nir_lower_mem_access_bit_sizes to cause them to be scalarized. However, one case was missing: the load-as-larger-vector case. In this case, we take small bit-sized constant-offset loads replace it with a 32-bit load and shuffle the result around as needed. For scratch, this case is much trickier to get right because it often emits vec2 or wider which we would then have to lower again. We did this for other load and store ops because, for lower bit-sizes we have to scalarize thanks to the byte scattered read/write instructions being scalar. However, for scratch we're not losing as much because we can't vectorize 32-bit loads and stores either. It's easier to just disallow it whenever we have to scalarize. Fixes: 53bfcdee "intel/fs: Implement the new load/store_scratch..." Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <mesa/mesa!6872>
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Dave Airlie authored
This adds support for building clover/llvmpipe and running the piglit CL tests on it. It uses the gl testing container, and add builds the libclc spirv libraries as part of that which requires the llvm spirv translator in the build container. It also builds the llvm spirv translator as part of the build root and creates a mesa build that builds clover for testing against it. It uses llvm 10 as the baseline. This drops bswap as it has an oob memory access with llvmpipe which cause flaky test results. phatk also seems flaky Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Part-of: <mesa/mesa!6901>
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- Oct 07, 2020
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Daniel Stone authored
For some reason, the radeonsi Tracie definition had the piano traces listed twice. Noted by @airlied Part-of: <mesa/mesa!7052>
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Faith Ekstrand authored
This puts it in a shared place where everyone can get at it. Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Dave Airlie authored
v2 (Jason Ekstrand): - Use the newly added nir_can_find_libclc() helper Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Faith Ekstrand authored
Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Dylan Baker authored
So that it's not tied directly to clover. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Dylan Baker authored
Acked-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Faith Ekstrand authored
If -b is specified, we don't add a null to the end of the char array. If -b is not specified, we assert that there are no nulls in the middle. Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Jesse Natalie authored
This keeps us from hitting the 65k string limit on MSVC Part-of: <mesa/mesa!7034>
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Jesse Natalie authored
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <mesa/mesa!7034>
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Dylan Baker authored
sys and string are unused, os is needed but not imported fixes: 412472da ("glsl: Add utility to convert text files to C strings") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <mesa/mesa!7034>
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Faith Ekstrand authored
This can be useful if you rsync an install between two machines and the paths don't perfectly match up. OpenGL drivers already work fine but anything which uses pipe-loader has a compile-time path. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <!7047>
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Faith Ekstrand authored
This commit enables clover support for iris. It is intended as a compiler developer tool and not as a new OpenCL implementation from Intel. If you want competent OpenCL, we have a different open-source driver for that built on our LLVM-based IGC compiler stack. However, using clover with iris is becoming increasingly useful as a compiler development tool and I'm getting tired of carrying the patches in a private branch. By default, clover will not initialize on iris. To enable clover, set the IRIS_ENABLE_CLOVER environment variable to "1" or "true". As we've done with the semi-sketchy platform support in ANV, it dumps a very loud WARNING to stderr when enabled. Use at your own risk. NOTE: To anyone intending to benchmark this, the performance is going to be terrible and that is expected. This is in no way representative of the Intel/NIR compiler stack. As it currently stands, clover passes -O0 to clang when compiling OpenCL C to make SPIRV-LLVM-Transator work. When compiling the SPIR-V, clover currently doesn't run any NIR optimizations before it lowers memory access so any NIR optimizations iris attempts to do are severely hampered. One day, clover will get a NIR optimization loop or the ability to hand things off to the driver per-lowering but today is not that day. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!7047>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!7047>
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Faith Ekstrand authored
The value specified in pipe_compute_state is in addition to the implicit value computed by NIR. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!7047>
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Faith Ekstrand authored
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <mesa/mesa!7047>
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