1. 13 Feb, 2020 12 commits
  2. 12 Feb, 2020 13 commits
  3. 11 Feb, 2020 15 commits
    • chadversary's avatar
      anv: Rename param make_surface::dev to device · 28614119
      chadversary authored
      
      
      Everywhere in anvil, each variable of type anv_device is named 'device',
      except this single instance. Rename it for consistency.
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Tested-by: Marge Bot <mesa/mesa!3773>
      Part-of: <mesa/mesa!3773>
      28614119
    • chadversary's avatar
      anv: Drop unused anv_image_get_surface_for_aspect_mask() · 84b791a4
      chadversary authored
      Replaced by anv_image.c:get_surface() in:
      
        commit a62a9793
      
      
        Author:     Lionel Landwerlin <lionel.g.landwerlin@intel.com>
        CommitDate: Fri Oct 6 16:32:20 2017 +0100
        Subject:    anv: enable multiple planes per image/imageView
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Part-of: <mesa/mesa!3773>
      84b791a4
    • Michel Dänzer's avatar
      gitlab-ci: Only use gstreamer runners for the s390x job for now · 23037627
      Michel Dänzer authored
      
      
      The fdo-packet-* runners keep hitting the (already quite long) timeouts
      for some of the tests, taking many times as long for them as the
      gstreamer runners.
      
      The fdo-gitlab-gce-runner3 runner would work as well, but it doesn't
      have any tags we could use.
      Acked-by: Daniel Stone's avatarDaniel Stone <daniels@collabora.com>
      Tested-by: Marge Bot <mesa/mesa!3760>
      Part-of: <mesa/mesa!3760>
      23037627
    • Samuel Pitoiset's avatar
      nir: do not use De Morgan's Law rules for flt and fge · 8e772807
      Samuel Pitoiset authored
      In presence of NaNs, "!(flt(a, b) && flt(c, d))" is NOT EQUAL
      to "fge(a, b) || fge(c, d)". These optimizations are unsafe for
      apps that rely on NaN behaviour.
      
      pipeline-db (GFX9/LLVM):
      Totals from affected shaders:
      SGPRS: 3176 -> 3136 (-1.26 %)
      VGPRS: 2188 -> 2144 (-2.01 %)
      Spilled SGPRs: 227 -> 169 (-25.55 %)
      Code Size: 150572 -> 151800 (0.82 %) bytes
      Max Waves: 307 -> 310 (0.98 %)
      
      pipeline-db (GFX9/ACO):
      Totals from affected shaders:
      SGPRS: 18744 -> 18744 (0.00 %)
      VGPRS: 15576 -> 15580 (0.03 %)
      Spilled SGPRs: 164 -> 164 (0.00 %)
      Code Size: 1573012 -> 1576492 (0.22 %) bytes
      Max Waves: 1534 -> 1532 (-0.13 %)
      
      Closes: mesa/mesa#2127
      Fixes: d1ed4ffe
      
       ("nir: Use De Morgan's Law on logic compounded comparisons")
      Signed-off-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      Reviewed-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Tested-by: Marge Bot <mesa/mesa!3696>
      Part-of: <mesa/mesa!3696>
      8e772807
    • Samuel Pitoiset's avatar
      aco: fix creating v_madak if v_mad_f32 has two sgpr literals · ddd76738
      Samuel Pitoiset authored
      Do not ignore that src1 can be a sgpr.
      
      Closes: mesa/mesa#2435
      
      
      Cc: <mesa-stable@lists.freedesktop.org>
      Signed-off-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      Reviewed-by: Rhys Perry's avatarRhys Perry <pendingchaos02@gmail.com>
      Tested-by: Marge Bot <mesa/mesa!3759>
      Part-of: <mesa/mesa!3759>
      ddd76738
    • Samuel Pitoiset's avatar
    • Samuel Pitoiset's avatar
    • Bas Nieuwenhuizen's avatar
      radv: Do not redundantly set the RB+ regs on pipeline switch. · 5b335e15
      Bas Nieuwenhuizen authored
      
      
      No significant perf changes seen on Bayonetta. (Changes are in the
      noise on my Raven Laptop)
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      Tested-by: Marge Bot <mesa/mesa!3735>
      Part-of: <mesa/mesa!3735>
      5b335e15
    • Vinson Lee's avatar
      panfrost: Remove unused anonymous enum variables. · 63345a35
      Vinson Lee authored
      This patch fix these build errors with GCC 10.
      
      /usr/bin/ld: src/gallium/drivers/panfrost/libpanfrost.a(pan_resource.c.o):src/panfrost/midgard/midgard_compile.h:52: multiple definition of `pan_sysval'; src/gallium/drivers/panfrost/libpanfrost.a(pan_screen.c.o):src/panfrost/midgard/midgard_compile.h:52: first defined here
      /usr/bin/ld: src/gallium/drivers/panfrost/libpanfrost.a(pan_resource.c.o):src/panfrost/midgard/midgard_compile.h:68: multiple definition of `pan_special_attributes'; src/gallium/drivers/panfrost/libpanfrost.a(pan_screen.c.o):src/panfrost/midgard/midgard_compile.h:68: first defined here
      
      Fixes: 7e8de5a7 ("panfrost: Implement system values")
      Fixes: 306800d7
      
       ("pan/midgard: Lower gl_VertexID/gl_InstanceID to attributes")
      Signed-off-by: Vinson Lee's avatarVinson Lee <vlee@freedesktop.org>
      Reviewed-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
      Tested-by: Marge Bot <mesa/mesa!3752>
      Part-of: <mesa/mesa!3752>
      63345a35
    • Bas Nieuwenhuizen's avatar
      radv: Optimize emitting index buffer changes. · 7792d774
      Bas Nieuwenhuizen authored
      
      
      Since the direct indexed draw packet has the address/count info
      inline, there is no sense in emitting the base and size.
      
      No real significant changes found during benchmarks.
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      Tested-by: Marge Bot <mesa/mesa!3466>
      Part-of: <mesa/mesa!3466>
      7792d774
    • Ian Romanick's avatar
      nir: Mark fmin and fmax as commutative and associative · 1d97d186
      Ian Romanick authored
      Per the resolution of Khronos GLSL issue 80
      (https://github.com/KhronosGroup/GLSL/issues/80
      
      ).  Spec updates have not
      landed yet, but I'll get to it soon. :)
      
      The extra hurt shaders on Gen8+ are a handful of shaders that see things like
      
          bcsel(fmin(b - a, a - c) >= 0, x, y)
      
      converted to
      
         bcsel(a >= b && c >= a, x, y)
      
      The former can be generated as a CSEL instruction.  If either b - a or a
      - c is used elsewhere in the shader, this saves an instruction.
      
      All Haswell+ platforms had similar results. (Ice Lake shown)
      total instructions in shared programs: 14550188 -> 14550048 (<.01%)
      instructions in affected programs: 12168 -> 12028 (-1.15%)
      helped: 30
      HURT: 3
      helped stats (abs) min: 1 max: 17 x̄: 4.77 x̃: 2
      helped stats (rel) min: 0.05% max: 3.85% x̄: 1.77% x̃: 1.80%
      HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
      HURT stats (rel)   min: 0.50% max: 0.50% x̄: 0.50% x̃: 0.50%
      95% mean confidence interval for instructions value: -6.15 -2.33
      95% mean confidence interval for instructions %-change: -2.00% -1.12%
      Instructions are helped.
      
      total cycles in shared programs: 203770286 -> 203771464 (<.01%)
      cycles in affected programs: 688466 -> 689644 (0.17%)
      helped: 172
      HURT: 220
      helped stats (abs) min: 1 max: 286 x̄: 12.15 x̃: 6
      helped stats (rel) min: 0.03% max: 5.97% x̄: 0.70% x̃: 0.35%
      HURT stats (abs)   min: 1 max: 578 x̄: 14.85 x̃: 6
      HURT stats (rel)   min: 0.03% max: 32.36% x̄: 1.21% x̃: 0.52%
      95% mean confidence interval for cycles value: -0.74 6.75
      95% mean confidence interval for cycles %-change: 0.15% 0.59%
      Inconclusive result (value mean confidence interval includes 0).
      
      total fills in shared programs: 4525 -> 4523 (-0.04%)
      fills in affected programs: 48 -> 46 (-4.17%)
      helped: 1
      HURT: 0
      
      Ivy Bridge
      total instructions in shared programs: 11858995 -> 11858898 (<.01%)
      instructions in affected programs: 10822 -> 10725 (-0.90%)
      helped: 25
      HURT: 13
      helped stats (abs) min: 1 max: 17 x̄: 5.32 x̃: 2
      helped stats (rel) min: 0.40% max: 5.00% x̄: 2.16% x̃: 1.85%
      HURT stats (abs)   min: 1 max: 15 x̄: 2.77 x̃: 2
      HURT stats (rel)   min: 0.47% max: 2.90% x̄: 1.83% x̃: 2.15%
      95% mean confidence interval for instructions value: -4.66 -0.45
      95% mean confidence interval for instructions %-change: -1.54% -0.05%
      Instructions are helped.
      
      total cycles in shared programs: 177947023 -> 177946880 (<.01%)
      cycles in affected programs: 822075 -> 821932 (-0.02%)
      helped: 157
      HURT: 175
      helped stats (abs) min: 1 max: 164 x̄: 13.17 x̃: 4
      helped stats (rel) min: 0.03% max: 6.72% x̄: 0.64% x̃: 0.17%
      HURT stats (abs)   min: 1 max: 308 x̄: 11.00 x̃: 4
      HURT stats (rel)   min: 0.03% max: 9.76% x̄: 0.70% x̃: 0.18%
      95% mean confidence interval for cycles value: -3.86 3.00
      95% mean confidence interval for cycles %-change: -0.09% 0.22%
      Inconclusive result (value mean confidence interval includes 0).
      
      total spills in shared programs: 4185 -> 4188 (0.07%)
      spills in affected programs: 146 -> 149 (2.05%)
      helped: 0
      HURT: 1
      
      total fills in shared programs: 5248 -> 5249 (0.02%)
      fills in affected programs: 347 -> 348 (0.29%)
      helped: 0
      HURT: 1
      
      Sandy Bridge
      total instructions in shared programs: 10680224 -> 10680144 (<.01%)
      instructions in affected programs: 4702 -> 4622 (-1.70%)
      helped: 15
      HURT: 3
      helped stats (abs) min: 1 max: 17 x̄: 5.53 x̃: 5
      helped stats (rel) min: 0.39% max: 4.76% x̄: 2.17% x̃: 1.67%
      HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
      HURT stats (rel)   min: 0.52% max: 0.52% x̄: 0.52% x̃: 0.52%
      95% mean confidence interval for instructions value: -7.24 -1.65
      95% mean confidence interval for instructions %-change: -2.55% -0.89%
      Instructions are helped.
      
      total cycles in shared programs: 152988780 -> 152985691 (<.01%)
      cycles in affected programs: 1072850 -> 1069761 (-0.29%)
      helped: 168
      HURT: 145
      helped stats (abs) min: 1 max: 592 x̄: 33.90 x̃: 12
      helped stats (rel) min: 0.02% max: 10.73% x̄: 0.90% x̃: 0.31%
      HURT stats (abs)   min: 1 max: 259 x̄: 17.98 x̃: 6
      HURT stats (rel)   min: 0.02% max: 8.17% x̄: 0.77% x̃: 0.19%
      95% mean confidence interval for cycles value: -17.95 -1.79
      95% mean confidence interval for cycles %-change: -0.34% 0.08%
      Inconclusive result (%-change mean confidence interval includes 0).
      
      Iron Lake and GM45 had similar results. (Iron Lake shown)
      total instructions in shared programs: 8107033 -> 8107025 (<.01%)
      instructions in affected programs: 696 -> 688 (-1.15%)
      helped: 5
      HURT: 0
      helped stats (abs) min: 1 max: 2 x̄: 1.60 x̃: 2
      helped stats (rel) min: 0.34% max: 7.14% x̄: 3.47% x̃: 4.65%
      95% mean confidence interval for instructions value: -2.28 -0.92
      95% mean confidence interval for instructions %-change: -7.22% 0.28%
      Inconclusive result (%-change mean confidence interval includes 0).
      
      total cycles in shared programs: 188348526 -> 188348404 (<.01%)
      cycles in affected programs: 33618 -> 33496 (-0.36%)
      helped: 23
      HURT: 0
      helped stats (abs) min: 2 max: 12 x̄: 5.30 x̃: 6
      helped stats (rel) min: 0.05% max: 1.83% x̄: 0.47% x̃: 0.51%
      95% mean confidence interval for cycles value: -6.70 -3.91
      95% mean confidence interval for cycles %-change: -0.64% -0.30%
      Cycles are helped.
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Part-of: <mesa/mesa!1359>
      1d97d186
    • Emma Anholt's avatar
      Revert "gallium: Fix big-endian addressing of non-bitmask array formats." · 1886dbfe
      Emma Anholt authored
      This reverts the functional part of commit
      d17ff2f7, leaving the unit test for
      mesa/pipe agreement on what's an array.
      
      The issue is that the util_channel_desc.shift values on array formats are
      not used for bit addressing in memory, they're bit addressing within a
      word treating a pixel of the format as a native type, as seen by
      llvmpipe's use of the values to do shifts (see
      lp_build_unpack_arith_rgba_aos() for example).  This means the values are
      nonsensical for 3-byte RGB, but then llvmpipe doesn't expose those formats
      so it works out.
      
      I still want to clean up our big-endian format handling at some point, but
      let's fix the s390x regression first, sort out our format unit tests in
      CI, then be able to refactor with confidence.
      
      Fixes: d17ff2f7
      
       ("gallium: Fix big-endian addressing of non-bitmask array formats.")
      Closes: #2472
      Acked-by: default avatarMarek Olšák <marek.olsak@amd.com>
      Tested-by: Marge Bot <mesa/mesa!3721>
      Part-of: <mesa/mesa!3721>
      1886dbfe
    • Marek Olšák's avatar
      st/mesa: optimize st_update_array with ALWAYSINLINE · 11db8e0e
      Marek Olšák authored
      
      
      The time spent in st_update_array is reduced by 5-10%.
      Reviewed-by: Mathias Fröhlich's avatarMathias Fröhlich <mathias.froehlich@web.de>
      Tested-by: Marge Bot <mesa/mesa!3766>
      Part-of: <mesa/mesa!3766>
      11db8e0e
    • Marek Olšák's avatar
    • Marek Olšák's avatar
      47d7e216