Commit da03e07c authored by Jordan Justen's avatar Jordan Justen Committed by Marge Bot
Browse files

iris: Emit CS Stall before Instruction Cache flush for gen12 WA



Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen's avatarJordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <mesa/mesa!3457>
parent b175effc
......@@ -6848,6 +6848,18 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
0, NULL, 0, 0);
}
/* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GEN_GEN == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
iris_emit_raw_pipe_control(batch,
"workaround: CS stall before instruction "
"cache invalidate",
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset,
imm);
}
if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
......
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