Commit 2969012d authored by Jordan Justen's avatar Jordan Justen Committed by Marge Bot
Browse files

anv: Emit CS Stall before Instruction Cache flush for gen12 WA



Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen's avatarJordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <mesa/mesa!3457>
Part-of: <mesa/mesa!3457>
parent da03e07c
......@@ -2022,6 +2022,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
}
/* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GEN_GEN == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
if ((GEN_GEN >= 8 && GEN_GEN <= 9) &&
(bits & ANV_PIPE_CS_STALL_BIT) &&
(bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) {
......
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