Fixes the following building error:

clang: error: no such file or directory: 'external/mesa/src/panfrost/bifrost/bi_tables.c'
clang: error: no input files

Fixes: b691aeaa

 ("pan/bi: Remove old IR opcode table")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

Fixes the following building error:

clang: error: no such file or directory: 'external/mesa/src/panfrost/bifrost/bi_special.c'
clang: error: no input files

Fixes: e5ec0dc1

 ("pan/bi: Remove NIR->old IR")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

Necessary for Android build after commit a1e150fc

Fixes: a1e150fc

 ("pan/bi: Remove old IR packs")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

Fixes the following building error:

clang: error: no such file or directory: 'external/mesa/src/panfrost/bifrost/bi_lower_combine.c'
clang: error: no input files

Fixes: 8b0d0a93

 ("pan/bi: Remove combine lowering")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

Necessary for Android build after commit 82328a52

Fixes: 82328a52

 ("pan/bi: Generate instruction packer for new IR")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

Fixes the following building error:

external/mesa/src/panfrost/bifrost/bifrost_compile.c:38:10: fatal error: 'bi_builder.h' file not found
         ^~~~~~~~~~~~~~
1 error generated.

Fixes: 8ef0d411

 ("pan/bi: Generate builder routines")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

To avoid building errors in Android

Fixes: 1893a380

 ("pan/bi: Generate instruction printer")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8294>

AMDVLK and AMDGPU-PRO also don't support these formats for texel
buffers and images.

Closes: mesa/mesa#3386


Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!8315>

Fix address calculation for indirect load_barycentric_at_sample on GFX6-8
with a uniform sample index.

A non-zero uniform sample index does not seem to be tested by CTS.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Gitlab: mesa/mesa#3966
Fixes: 93c8ebfa ("aco: Initial commit of independent AMD compiler")
Part-of: <mesa/mesa!8302>

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: cffc1d90 ("pan/bi: Add staging register counts to ISA.xml")
Reported-by: Icecream95
Tested-by: macc24
Part-of: <mesa/mesa!8310>

This feature doesn't seem to work properly on Midgard, and is flagged
as unsupported on Bifrost v6.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

When using 3D AFBC, all headers are placed at the beginning instead of
being interleaved with each surface body, which forces us to adjust
the calculation in that case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Take 3D/array textures into accound when checking for entire overwrite.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

This way we can load uninitialized AFBC surfaces without causing GPU
faults.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

If we don't do that we don't account for CRC buffers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Bifrost and Midgard render target and ZS extension descriptors are a bit
different, adjust the code to take those differences into account.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

R16_UNORM isn't compatible with AFBC, we need to use the native Z16
format if we want to allow AFBC on those resources.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

This field takes 4 bits, not 2.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

On Bifrost v7, AFBC textures can't be used with a non-identity component
order. Let's patch the format so the component order is always RGB[A].
That means we're lying about the internal format, but that shouldn't be
a problem as long as we don't share the resource.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

And let the function translate it to a mali swizzle. This way we will
be able to adjust the swizzle if needed.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

AFBC strides are different from tiled/linear stride and we need to
use the value defined in slice.afbc.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Those are needed for render target and texture descriptors and can't be
easily extracted from the other fields present in panfrost_slice

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

3D AFBC textures have their AFBC headers grouped together at the
beginning of the buffer which means the header_size should be multiplied
by the depth. 2D arrays have their AFBC headers placed at the beginning
of each slice, meaning that the slice size should take them into account.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

So we can add more AFBC related fields under this struct.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Group the slices, dimension, modifier and array stride in a an object
representing the image layout. This way we shrink the number of
arguments passed to various pan_texture helpers and simplifies some
of the logic along the way.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Texture depth and MSAA are two different concepts even if they are
exclusive on Mali GPUs (depth field is repurposed for sample index
there). Let's not mix them and adjust the slice_full_size calculation
to take both into account.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Suggested-by: Icecream95
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

This field is encoding the stride between two consecutive surface
in a 3D texture. Let's use a name reflecting that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

There's no reason to keep both now that the internal logic has been
deduplicated.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Bifrost has a few more compression flags that are worth specifying.
Extend panfrost_compression_tag() to deal with those too.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

So we can soon use the same path for Bifrost and Midgard.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

The only reason we have two different functions to prepare the texture
payload is the different ordering between pre-v7 and v7+ GPUs. Abstract
the surface iteration so we can merge panfrost_emit_texture_payload_v7()
and panfrost_emit_texture_payload().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

We will need it to merge some of the Bifrost and Midgard logic.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

There's no reason to have the checksum_bo at the slice level since there
can only be one external CRC BO per resource. Move this field to the
panfrost_resource struct.

Suggested-by: Icecream95
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8125>

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <mesa/mesa!8151>