Commit e03a056a authored by Icecream95's avatar Icecream95 Committed by Alyssa Rosenzweig
Browse files

pan/mdg: Try scheduling load/store ops in pairs

If there are an even number of load/store ops to be scheduled, and
only one load/store op is available for scheduling, try using another
instruction type.

Helps bundle count at the cost of register pressure.

total instructions in shared programs: 333405 -> 333599 (0.06%)
instructions in affected programs: 27576 -> 27770 (0.70%)
helped: 43
HURT: 69
helped stats (abs) min: 1 max: 61 x̄: 5.49 x̃: 1
helped stats (rel) min: 0.18% max: 11.71% x̄: 2.27% x̃: 1.75%
HURT stats (abs)   min: 1 max: 95 x̄: 6.23 x̃: 2
HURT stats (rel)   min: 0.06% max: 32.42% x̄: 2.59% x̃: 1.53%
95% mean confidence interval for instructions value: -0.93 4.40
95% mean confidence interval for instructions %-change: -0.09% 1.53%
Inconclusive result (value mean confidence interval includes 0).

total bundles in shared programs: 155785 -> 152371 (-2.19%)
bundles in affected programs: 83689 -> 80275 (-4.08%)
helped: 2538
HURT: 110
helped stats (abs) min: 1 max: 59 x̄: 1.53 x̃: 1
helped stats (rel) min: 0.14% max: 22.52% x̄: 8.71% x̃: 7.69%
HURT stats (abs)   min: 1 max: 92 x̄: 4.32 x̃: 1
HURT stats (rel)   min: 0.21% max: 55.76% x̄: 4.61% x̃: 2.86%
95% mean confidence interval for bundles value: -1.41 -1.17
95% mean confidence interval for bundles %-change: -8.37% -7.94%
Bundles are helped.

total quadwords in shared programs: 264143 -> 260520 (-1.37%)
quadwords in affected programs: 141705 -> 138082 (-2.56%)
helped: 2560
HURT: 96
helped stats (abs) min: 1 max: 15 x̄: 1.49 x̃: 1
helped stats (rel) min: 0.06% max: 14.29% x̄: 5.62% x̃: 5.00%
HURT stats (abs)   min: 1 max: 11 x̄: 2.02 x̃: 2
HURT stats (rel)   min: 0.12% max: 6.20% x̄: 1.94% x̃: 1.47%
95% mean confidence interval for quadwords value: -1.42 -1.31
95% mean confidence interval for quadwords %-change: -5.50% -5.20%
Quadwords are helped.

total registers in shared programs: 21709 -> 22156 (2.06%)
registers in affected programs: 2684 -> 3131 (16.65%)
helped: 55
HURT: 470
helped stats (abs) min: 1 max: 2 x̄: 1.05 x̃: 1
helped stats (rel) min: 6.67% max: 40.00% x̄: 15.37% x̃: 14.29%
HURT stats (abs)   min: 1 max: 4 x̄: 1.07 x̃: 1
HURT stats (rel)   min: 6.67% max: 100.00% x̄: 31.63% x̃: 25.00%
95% mean confidence interval for registers value: 0.79 0.91
95% mean confidence interval for registers %-change: 24.69% 28.72%
Registers are HURT.

total threads in shared programs: 24450 -> 24360 (-0.37%)
threads in affected programs: 234 -> 144 (-38.46%)
helped: 12
HURT: 63
helped stats (abs) min: 1 max: 2 x̄: 1.50 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 1 max: 2 x̄: 1.71 x̃: 2
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.49 -0.91
95% mean confidence interval for threads %-change: -38.74% -13.26%
Threads are [HURT].

total loops in shared programs: 286 -> 286 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 521 -> 593 (13.82%)
spills in affected programs: 260 -> 332 (27.69%)
helped: 8
HURT: 9

total fills in shared programs: 1598 -> 1659 (3.82%)
fills in affected programs: 839 -> 900 (7.27%)
helped: 9
HURT: 10
parent 91bd4fc6
Pipeline #315888 waiting for manual action with stages
......@@ -783,7 +783,8 @@ static unsigned
mir_choose_bundle(
midgard_instruction **instructions,
uint16_t *liveness,
BITSET_WORD *worklist, unsigned count)
BITSET_WORD *worklist, unsigned count,
unsigned num_ldst)
{
/* At the moment, our algorithm is very simple - use the bundle of the
* best instruction, regardless of what else could be scheduled
......@@ -797,6 +798,25 @@ mir_choose_bundle(
midgard_instruction *chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
if (chosen && chosen->type == TAG_LOAD_STORE_4 && !(num_ldst % 2)) {
/* Try to schedule load/store ops in pairs */
predicate.exclude = chosen->dest;
predicate.tag = TAG_LOAD_STORE_4;
chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
if (chosen)
return TAG_LOAD_STORE_4;
predicate.tag = ~0;
chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
if (chosen)
return chosen->type;
else
return TAG_LOAD_STORE_4;
}
if (chosen)
return chosen->type;
else
......@@ -1016,7 +1036,8 @@ static midgard_bundle
mir_schedule_ldst(
midgard_instruction **instructions,
uint16_t *liveness,
BITSET_WORD *worklist, unsigned len)
BITSET_WORD *worklist, unsigned len,
unsigned *num_ldst)
{
struct midgard_predicate predicate = {
.tag = TAG_LOAD_STORE_4,
......@@ -1038,6 +1059,8 @@ mir_schedule_ldst(
.instructions = { ins, pair }
};
*num_ldst -= out.instruction_count;
/* We have to update the worklist atomically, since the two
* instructions run concurrently (TODO: verify it's not pipelined) */
......@@ -1401,19 +1424,27 @@ schedule_block(compiler_context *ctx, midgard_block *block)
uint16_t *liveness = calloc(node_count, 2);
mir_initialize_worklist(worklist, instructions, len);
/* Count the number of load/store instructions so we know when it's
* worth trying to schedule them in pairs. */
unsigned num_ldst = 0;
for (unsigned i = 0; i < len; ++i) {
if (instructions[i]->type == TAG_LOAD_STORE_4)
++num_ldst;
}
struct util_dynarray bundles;
util_dynarray_init(&bundles, NULL);
block->quadword_count = 0;
for (;;) {
unsigned tag = mir_choose_bundle(instructions, liveness, worklist, len);
unsigned tag = mir_choose_bundle(instructions, liveness, worklist, len, num_ldst);
midgard_bundle bundle;
if (tag == TAG_TEXTURE_4)
bundle = mir_schedule_texture(instructions, liveness, worklist, len, ctx->stage != MESA_SHADER_FRAGMENT);
else if (tag == TAG_LOAD_STORE_4)
bundle = mir_schedule_ldst(instructions, liveness, worklist, len);
bundle = mir_schedule_ldst(instructions, liveness, worklist, len, &num_ldst);
else if (tag == TAG_ALU_4)
bundle = mir_schedule_alu(ctx, instructions, liveness, worklist, len);
else
......@@ -1423,6 +1454,8 @@ schedule_block(compiler_context *ctx, midgard_block *block)
block->quadword_count += midgard_tag_props[bundle.tag].size;
}
assert(num_ldst == 0);
/* We emitted bundles backwards; copy into the block in reverse-order */
util_dynarray_init(&block->bundles, block);
......
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