Commit 6c530ad1 authored by Chris Wilson's avatar Chris Wilson 🤔 Committed by Kenneth Graunke
Browse files

i965: Reduce passing 2x32b of reloc_domains to 2 bits



The kernel only cares about whether the object is to be written to or
not, only reduces (reloc.read_domains, reloc.write_domain) down to just
!!reloc.write_domain. When we use NO_RELOC, the kernel doesn't even read
those relocs and instead userspace has to pass that information in the
execobject.flags. We can simplify our reloc api by also removing the
unused read/write domains and only pass the resultant flags.

The caveat to the above are when we need to make the kernel aware that
certain objects need to take into account different work arounds.
Previously, this was done using the magic (INSTRUCTION, INSTRUCTION)
reloc domains. NO_RELOC requires this to be passed in the execobject
flags as well, and now we push that up the callstack.

The API is more compact, more expressive of what happens underneath, but
unfortunately requires more knowledge of the system at the point of use.
Conversely it also means that knowledge is specific and not generally
applied and so not overused.

   text	   data	    bss	    dec	    hex	filename
8502991	 356912	 424944	9284847	 8dacef	lib/i965_dri.so (before)
8500455	 356912	 424944	9282311	 8da307	lib/i965_dri.so (after)

v2: (by Ken) Rebase.
Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
parent 2aacd22c
......@@ -92,8 +92,7 @@ void blorp_batch_finish(struct blorp_batch *batch);
struct blorp_address {
void *buffer;
uint32_t read_domains;
uint32_t write_domain;
unsigned reloc_flags;
uint32_t offset;
};
......
......@@ -69,7 +69,7 @@ brw_upload_binding_table(struct brw_context *brw,
brw, &stage_state->surf_offset[
prog_data->binding_table.shader_time_start],
brw->shader_time.bo, 0, ISL_FORMAT_RAW,
brw->shader_time.bo->size, 1, true);
brw->shader_time.bo->size, 1, RELOC_WRITE);
}
uint32_t *bind =
brw_state_batch(brw, prog_data->binding_table.size_bytes,
......
......@@ -150,9 +150,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->addr = (struct blorp_address) {
.buffer = mt->bo,
.offset = mt->offset,
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
};
surf->aux_usage = aux_usage;
......@@ -175,9 +173,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->aux_surf = aux_surf;
surf->aux_addr = (struct blorp_address) {
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
};
if (mt->mcs_buf) {
......
......@@ -40,15 +40,9 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
struct brw_bo *bo = brw->compute.num_work_groups_bo;
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
I915_GEM_DOMAIN_VERTEX, 0,
indirect_offset + 0);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo,
I915_GEM_DOMAIN_VERTEX, 0,
indirect_offset + 4);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo,
I915_GEM_DOMAIN_VERTEX, 0,
indirect_offset + 8);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
if (brw->gen > 7)
return;
......@@ -65,9 +59,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_x_size into SRC0 */
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
indirect_offset + 0);
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
/* predicate = (compute_dispatch_indirect_x_size == 0); */
BEGIN_BATCH(1);
......@@ -78,9 +70,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_y_size into SRC0 */
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
indirect_offset + 4);
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
BEGIN_BATCH(1);
......@@ -91,9 +81,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_z_size into SRC0 */
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
indirect_offset + 8);
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
BEGIN_BATCH(1);
......
......@@ -87,18 +87,8 @@ set_predicate_for_occlusion_query(struct brw_context *brw,
*/
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
brw_load_register_mem64(brw,
MI_PREDICATE_SRC0,
query->bo,
I915_GEM_DOMAIN_INSTRUCTION,
0, /* write domain */
0 /* offset */);
brw_load_register_mem64(brw,
MI_PREDICATE_SRC1,
query->bo,
I915_GEM_DOMAIN_INSTRUCTION,
0, /* write domain */
8 /* offset */);
brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */);
}
static void
......
......@@ -458,6 +458,7 @@ struct intel_batchbuffer {
struct drm_i915_gem_relocation_entry *relocs;
int reloc_count;
int reloc_array_size;
unsigned int valid_reloc_flags;
/** The validation list */
struct drm_i915_gem_exec_object2 *validation_list;
......@@ -1321,12 +1322,10 @@ bool brw_check_conditional_render(struct brw_context *brw);
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_store_register_mem32(struct brw_context *brw,
struct brw_bo *bo, uint32_t reg, uint32_t offset);
......
......@@ -301,8 +301,7 @@ emit:
OUT_BATCH(0);
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
OUT_RELOC(brw->curbe.curbe_bo, 0,
(brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
......
......@@ -205,7 +205,6 @@ brw_emit_prim(struct brw_context *brw,
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT,
xfb_obj->prim_count_bo,
I915_GEM_DOMAIN_VERTEX, 0,
stream * sizeof(uint32_t));
BEGIN_BATCH(9);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (9 - 2));
......@@ -227,25 +226,19 @@ brw_emit_prim(struct brw_context *brw,
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 0);
brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 4);
brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 8);
if (prim->indexed) {
brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 12);
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 16);
} else {
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 12);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
......
......@@ -63,21 +63,15 @@ upload_pipelined_state_pointers(struct brw_context *brw)
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->vs.base.state_offset);
OUT_RELOC(brw->batch.bo, 0, brw->vs.base.state_offset);
if (brw->ff_gs.prog_active)
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->ff_gs.state_offset | 1);
OUT_RELOC(brw->batch.bo, 0, brw->ff_gs.state_offset | 1);
else
OUT_BATCH(0);
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->clip.state_offset | 1);
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->sf.state_offset);
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->wm.base.state_offset);
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->cc.state_offset);
OUT_RELOC(brw->batch.bo, 0, brw->clip.state_offset | 1);
OUT_RELOC(brw->batch.bo, 0, brw->sf.state_offset);
OUT_RELOC(brw->batch.bo, 0, brw->wm.base.state_offset);
OUT_RELOC(brw->batch.bo, 0, brw->cc.state_offset);
ADVANCE_BATCH();
brw->ctx.NewDriverState |= BRW_NEW_PSP;
......@@ -387,9 +381,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
(depth_surface_type << 29));
if (depth_mt) {
OUT_RELOC(depth_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
depth_offset);
OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset);
} else {
OUT_BATCH(0);
}
......@@ -636,18 +628,14 @@ brw_upload_state_base_address(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
mocs_wb << 4 | 1);
OUT_RELOC64(brw->batch.bo, 0, mocs_wb << 4 | 1);
/* Dynamic state base address: */
OUT_RELOC64(brw->batch.bo,
I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
mocs_wb << 4 | 1);
OUT_RELOC64(brw->batch.bo, 0, mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
mocs_wb << 4 | 1);
OUT_RELOC64(brw->cache.bo, 0, mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
......@@ -675,7 +663,7 @@ brw_upload_state_base_address(struct brw_context *brw)
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
OUT_RELOC(brw->batch.bo, 0, 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
......@@ -686,12 +674,12 @@ brw_upload_state_base_address(struct brw_context *brw)
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
OUT_RELOC(brw->batch.bo, 0, 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
1); /* Instruction base address: shader kernels (incl. SIP) */
/* Instruction base address: shader kernels (incl. SIP) */
OUT_RELOC(brw->cache.bo, 0, 1);
OUT_BATCH(1); /* General state upper bound */
/* Dynamic state upper bound. Although the documentation says that
......@@ -707,11 +695,9 @@ brw_upload_state_base_address(struct brw_context *brw)
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
1); /* Surface state base address */
OUT_RELOC(brw->batch.bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
1); /* Instruction base address */
OUT_RELOC(brw->cache.bo, 0, 1); /* Instruction base address */
OUT_BATCH(0xfffff001); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
......@@ -720,8 +706,7 @@ brw_upload_state_base_address(struct brw_context *brw)
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
1); /* Surface state base address */
OUT_RELOC(brw->batch.bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
......
......@@ -109,8 +109,7 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);
if (bo) {
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION, offset);
OUT_RELOC64(bo, RELOC_WRITE, offset);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
......@@ -141,8 +140,7 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(flags);
if (bo) {
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
gen6_gtt | offset);
OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, gen6_gtt | offset);
} else {
OUT_BATCH(0);
}
......@@ -153,8 +151,7 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
if (bo) {
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
OUT_RELOC(bo, RELOC_WRITE, PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
} else {
OUT_BATCH(0);
}
......@@ -409,8 +406,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
* 3DPRIMITIVE when needed anyway.
*/
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE,
brw->workaround_bo,
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
brw->workaround_bo, 0);
}
} else {
/* On gen4-5, a regular pipe control seems to suffice. */
......
......@@ -216,7 +216,7 @@ void brw_emit_buffer_surface_state(struct brw_context *brw,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
bool rw);
unsigned reloc_flags);
void brw_update_texture_surface(struct gl_context *ctx,
unsigned unit, uint32_t *surf_offset,
......
......@@ -133,7 +133,7 @@ brw_emit_surface_state(struct brw_context *brw,
GLenum target, struct isl_view view,
enum isl_aux_usage aux_usage,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
unsigned reloc_flags)
{
uint32_t tile_x = mt->level[0].level_x;
uint32_t tile_y = mt->level[0].level_y;
......@@ -182,7 +182,7 @@ brw_emit_surface_state(struct brw_context *brw,
isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view,
.address = brw_emit_reloc(&brw->batch,
*surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset, read_domains, write_domains),
mt->bo, offset, reloc_flags),
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
......@@ -202,7 +202,7 @@ brw_emit_surface_state(struct brw_context *brw,
*surf_offset +
brw->isl_dev.ss.aux_addr_offset,
aux_bo, *aux_addr,
read_domains, write_domains);
reloc_flags);
}
}
......@@ -247,8 +247,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
rb_mocs[brw->gen],
&offset, surf_index,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
RELOC_WRITE);
return offset;
}
......@@ -592,7 +591,7 @@ brw_update_texture_surface(struct gl_context *ctx,
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
0);
}
}
......@@ -604,7 +603,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
bool rw)
unsigned reloc_flags)
{
uint32_t *dw = brw_state_batch(brw,
brw->isl_dev.ss.size,
......@@ -616,8 +615,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
brw_emit_reloc(&brw->batch,
*out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0)),
reloc_flags),
.size = buffer_size,
.format = surface_format,
.stride = pitch,
......@@ -673,7 +671,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
isl_format,
size,
texel_size,
false /* rw */);
0);
}
/**
......@@ -689,7 +687,7 @@ brw_create_constant_surface(struct brw_context *brw,
{
brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
ISL_FORMAT_R32G32B32A32_FLOAT,
size, 1, false);
size, 1, 0);
}
/**
......@@ -711,7 +709,7 @@ brw_create_buffer_surface(struct brw_context *brw,
*/
brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
ISL_FORMAT_RAW,
size, 1, true);
size, 1, RELOC_WRITE);
}
/**
......@@ -785,8 +783,7 @@ brw_update_sol_surface(struct brw_context *brw,
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
surf[1] = brw_emit_reloc(&brw->batch,
*out_offset + 4, bo, offset_bytes,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
*out_offset + 4, bo, offset_bytes, RELOC_WRITE);
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
......@@ -901,8 +898,8 @@ brw_emit_null_surface_state(struct brw_context *brw,
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
surf[1] = !bo ? 0 :
brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0, RELOC_WRITE);
surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
......@@ -976,7 +973,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
intel_renderbuffer_get_tile_offsets(irb,
&tile_x,
&tile_y),
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
RELOC_WRITE);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
......@@ -1160,7 +1157,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
brw_emit_surface_state(brw, irb->mt, target, view, aux_usage,
tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
0);
} else {
brw->vtbl.emit_null_surface_state(
......@@ -1453,7 +1450,8 @@ brw_upload_abo_surfaces(struct brw_context *brw,
brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
binding->Offset, ISL_FORMAT_RAW,
bo->size - binding->Offset, 1, true);
bo->size - binding->Offset, 1,
RELOC_WRITE);
}
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
......@@ -1614,7 +1612,7 @@ update_image_surface(struct brw_context *brw,
brw_emit_buffer_surface_state(
brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
format, intel_obj->Base.Size, texel_size,
access != GL_READ_ONLY);
access != GL_READ_ONLY ? RELOC_WRITE : 0);
update_buffer_image_param(brw, u, surface_idx, param);
......@@ -1638,7 +1636,7 @@ update_image_surface(struct brw_context *brw,
brw_emit_buffer_surface_state(
brw, surf_offset, mt->bo, mt->offset,
format, mt->bo->size - mt->offset, 1 /* pitch */,
access != GL_READ_ONLY);
access != GL_READ_ONLY ? RELOC_WRITE : 0);
} else {
const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
......@@ -1649,9 +1647,7 @@ update_image_surface(struct brw_context *brw,
brw_emit_surface_state(brw, mt, mt->target, view,
ISL_AUX_USAGE_NONE, tex_mocs[brw->gen],
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER,
access == GL_READ_ONLY ? 0 :
I915_GEM_DOMAIN_SAMPLER);
access == GL_READ_ONLY ? 0 : RELOC_WRITE);
}
isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view);
......@@ -1766,7 +1762,8 @@ brw_upload_cs_work_groups_surface(struct brw_context *brw)
brw_emit_buffer_surface_state(brw, surf_offset,
bo, bo_offset,
ISL_FORMAT_RAW,
3 * sizeof(GLuint), 1, true);
3 * sizeof(GLuint), 1,
RELOC_WRITE);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
}
......
......@@ -30,8 +30,6 @@ dynamic_state_address(struct blorp_batch *batch, uint32_t offset)
return (struct blorp_address) {
.buffer = brw->batch.bo,
.offset = offset,
.write_domain = 0,
.read_domains = I915_GEM_DOMAIN_INSTRUCTION,
};
}
......@@ -44,8 +42,6 @@ instruction_state_address(struct blorp_batch *batch, uint32_t offset)
return (struct blorp_address) {
.buffer = brw->cache.bo,
.offset = offset,
.write_domain = 0,
.read_domains = I915_GEM_DOMAIN_INSTRUCTION,
};
}
......
......@@ -122,9 +122,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
OUT_RELOC(depth_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
} else {
OUT_BATCH(0);
}
......@@ -168,9 +166,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
OUT_RELOC(depth_mt->hiz_buf->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
......@@ -192,9 +188,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(stencil_mt->surf.row_pitch - 1);
OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
......
......@@ -114,9 +114,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
OUT_RELOC(depth_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
} else {
OUT_BATCH(0);
}
......@@ -151,10 +149,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(depth_mt->hiz_buf->pitch - 1));
OUT_RELOC(depth_mt->hiz_buf->bo,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
0);
OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
......@@ -173,9 +168,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(enabled |
mocs << 25 |
(stencil_mt->surf.row_pitch - 1));
OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
......
......@@ -120,9 +120,7 @@ gen7_pause_transform_feedback(struct gl_context *ctx,