Merge requests · Mesa · GitLab

Due to an influx of spam, we have had to impose restrictions on new accounts. Please see this wiki page for instructions on how to get full permissions. Sorry for the inconvenience.

radv: rework whether the global BO list should be enabled based on features

mesa!32718 · created Dec 19, 2024 by Samuel Pitoiset
RADV
- Merged
- 4
updated Dec 20, 2024
ci/windows: Always include windows-msvc in scheduled pipelines

mesa!32717 · created Dec 19, 2024 by Valentine Burley
CI
- Merged
- Approved
updated Dec 19, 2024
iris: Check that mem_fence_bo was created

mesa!32716 · created Dec 19, 2024 by Jordan Justen
iris
- Merged
- 1
updated Dec 19, 2024
mesa: enable GL name reuse by default for all drivers except virgl, rework the enablement

mesa!32715 · created Dec 19, 2024 by Marek Olšák
mesa
- Merged
- 13
- 2
updated Jan 14, 2025
brw: Don't rely on SIMD splitting in opt_combine_convergent_txfs

mesa!32714 · created Dec 19, 2024 by Kenneth Graunke
intel-brw
- Merged
- 1
updated Dec 19, 2024
radeonsi: fixes, cleanups, optimizations, update fails/flakes (e.g. fix alpha-to-coverage, kill Z/stencil outputs, gfx12 streamout fix and optimization)

mesa!32713 · created Dec 19, 2024 by Marek Olšák
RADV radeonsi
- Merged
- 5
updated Dec 26, 2024
intel/brw/xe2+: Do not use $.dst or $.src SWSB annotations in SENDs

mesa!32712 · created Dec 19, 2024 by Caio Oliveira
intel-brw
- Merged
- 2
updated Jan 07, 2025
intel/brw: Use variable instead of manually count the passes

mesa!32709 · created Dec 18, 2024 by Caio Oliveira
intel-brw intel-compiler
- Merged
- 5
updated Dec 20, 2024
intel: Expose Shader Hashes for Compute/Draw stages

mesa!32708 · created Dec 18, 2024 by michaelonchrome
ANV hasvk intel iris
- Merged
- 24
updated Jan 10, 2025
amdgpu: add new marketing names

drm!403 · created Dec 18, 2024 by Alex Deucher
AMD
updated Jan 09, 2025
radeonsi/vcn: Enable write combine for decode

mesa!32707 · created Dec 18, 2024 by David Rosca
radeonsi
- Merged
- 1
updated Dec 19, 2024
virgl: Update virgl_hw.h from virglrenderer

mesa!32706 · created Dec 18, 2024 by Corentin Noël
virgl
- Merged
- 1
updated Jan 07, 2025
radeonsi/vcn: Decode fence cleanup + remove PIPE_DEFAULT_DECODER_FEEDBACK_TIMEOUT_NS

mesa!32705 · created Dec 18, 2024 by David Rosca
gallium radeonsi
- Merged
- 1
updated Dec 20, 2024
ci/windows: Bump the number of tests per group and add a nightly full job

mesa!32704 · created Dec 18, 2024 by Valentine Burley
CI CI-Expectations dozen
- Merged
- 5
- Approved
updated Dec 19, 2024
vc4: ensure sharing tiled resources are of proper format

mesa!32703 · created Dec 18, 2024 by Juan A. Suárez
vc4
- Merged
- 3
updated Dec 23, 2024
radv: cleanup emulated queries

mesa!32702 · created Dec 18, 2024 by Samuel Pitoiset
RADV
- Merged
- 1
updated Dec 19, 2024
radv: fix regressions with mesh/task shader queries

mesa!32701 · created Dec 18, 2024 by Samuel Pitoiset
RADV
- Merged
- 1
updated Dec 19, 2024
vkgears: add win32 wsi-support

demos!209 · created Dec 18, 2024 by Erik Faye-Lund
Vulkan Windows
- Merged
- 13
updated Jan 16, 2025
nir/opt_load_store_vectorize: make hole_size signed to indicate overlapping loads

mesa!32699 · created Dec 18, 2024 by Marek Olšák
NIR
- Merged
- 5
updated Jan 01, 2025
radeonsi, spirv-to-nir: piglit and glcts fixes

mesa!32698 · created Dec 18, 2024 by Pierre-Eric Pelloux-Prayer
AMD common CI-Expectations mesa radeonsi
- Merged
- 16
updated Jan 09, 2025

Prev
1
…
10
11
12
13
14
15
16
17
18
…
1527
Next