• Samuel Iglesias Gonsálvez's avatar
    i965/vec4: fix register width for DF VGRF and UNIFORM · 0b9d7ea7
    Samuel Iglesias Gonsálvez authored
    On gen7, the swizzles used in DF align16 instructions works for element
    size of 32 bits, so we can address only 2 consecutive DFs. As we assumed that
    in the rest of the code and prepare the instructions for this (scalarize_df()),
    we need to set it to two again.
    
    However, for DF align1 instructions, a width of 2 is wrong as we are not
    reading the data we want. For example, an uniform would have a region of
    <0, 2, 1> so it would repeat the first 2 DFs, when we wanted to access
    to the first 4.
    
    This patch sets the default one to 4 and then modifies the width of
    align16 instruction's DF sources when we translate the logical swizzle
    to the physical one.
    
    v2:
    - Remove conditional (Curro).
    Signed-off-by: Samuel Iglesias Gonsálvez's avatarSamuel Iglesias Gonsálvez <siglesias@igalia.com>
    Cc: "17.1" <mesa-stable@lists.freedesktop.org>
    Reviewed-by: Francisco Jerez's avatarFrancisco Jerez <currojerez@riseup.net>
    (cherry picked from commit aaeb1c99)
    0b9d7ea7
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