Commit 7c71ef3a authored by Eric Anholt's avatar Eric Anholt

[intel] Move bufmgr back to context instead of screen, fixing glthreads.

Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes.  It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965).  The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
parent 00e10a13
......@@ -60,6 +60,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "intel_decode.h"
#include "intel_bufmgr_ttm.h"
#include "drirenderbuffer.h"
#include "vblank.h"
......@@ -291,6 +292,81 @@ intelFinish(GLcontext * ctx)
}
}
/** Driver-specific fence emit implementation for the fake memory manager. */
static unsigned int
intel_fence_emit(void *private)
{
struct intel_context *intel = (struct intel_context *)private;
unsigned int fence;
/* XXX: Need to emit a flush, if we haven't already (at least with the
* current batchbuffer implementation, we have).
*/
fence = intelEmitIrqLocked(intel);
return fence;
}
/** Driver-specific fence wait implementation for the fake memory manager. */
static int
intel_fence_wait(void *private, unsigned int cookie)
{
struct intel_context *intel = (struct intel_context *)private;
intelWaitIrq(intel, cookie);
return 0;
}
static GLboolean
intel_init_bufmgr(struct intel_context *intel)
{
intelScreenPrivate *intelScreen = intel->intelScreen;
GLboolean ttm_disable = getenv("INTEL_NO_TTM") != NULL;
/* If we've got a new enough DDX that's initializing TTM and giving us
* object handles for the shared buffers, use that.
*/
intel->ttm = GL_FALSE;
if (!ttm_disable &&
intel->intelScreen->driScrnPriv->ddx_version.minor >= 9 &&
intel->intelScreen->drmMinor >= 11 &&
intel->intelScreen->front.bo_handle != -1)
{
intel->bufmgr = intel_bufmgr_ttm_init(intel->driFd,
DRM_FENCE_TYPE_EXE,
DRM_FENCE_TYPE_EXE |
DRM_I915_FENCE_TYPE_RW,
BATCH_SZ);
if (intel->bufmgr != NULL)
intel->ttm = GL_TRUE;
}
/* Otherwise, use the classic buffer manager. */
if (intel->bufmgr == NULL) {
if (ttm_disable) {
fprintf(stderr, "TTM buffer manager disabled. Using classic.\n");
} else {
fprintf(stderr, "Failed to initialize TTM buffer manager. "
"Falling back to classic.\n");
}
if (intelScreen->tex.size == 0) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return GL_FALSE;
}
intel->bufmgr = dri_bufmgr_fake_init(intelScreen->tex.offset,
intelScreen->tex.map,
intelScreen->tex.size,
intel_fence_emit,
intel_fence_wait,
intel);
}
return GL_TRUE;
}
void
intelInitDriverFunctions(struct dd_function_table *functions)
......@@ -338,9 +414,22 @@ intelInitContext(struct intel_context *intel,
intel->driScreen = sPriv;
intel->sarea = saPriv;
/* Dri stuff */
intel->hHWContext = driContextPriv->hHWContext;
intel->driFd = sPriv->fd;
intel->driHwLock = (drmLock *) & sPriv->pSAREA->lock;
intel->width = intelScreen->width;
intel->height = intelScreen->height;
if (intelScreen->deviceID == PCI_CHIP_I865_G)
intel->maxBatchSize = 4096;
else
intel->maxBatchSize = BATCH_SZ;
if (!intel_init_bufmgr(intel))
return GL_FALSE;
if (!lockMutexInit) {
lockMutexInit = GL_TRUE;
_glthread_INIT_MUTEX(lockMutex);
......@@ -391,11 +480,6 @@ intelInitContext(struct intel_context *intel,
_swrast_allow_pixel_fog(ctx, GL_FALSE);
_swrast_allow_vertex_fog(ctx, GL_TRUE);
/* Dri stuff */
intel->hHWContext = driContextPriv->hHWContext;
intel->driFd = sPriv->fd;
intel->driHwLock = (drmLock *) & sPriv->pSAREA->lock;
intel->hw_stipple = 1;
/* XXX FBO: this doesn't seem to be used anywhere */
......@@ -436,9 +520,10 @@ intelInitContext(struct intel_context *intel,
/* GL_TRUE, */
GL_FALSE);
if (intelScreen->ttm)
if (intel->ttm)
driInitExtensions(ctx, ttm_extensions, GL_FALSE);
intel_recreate_static_regions(intel);
intel->batch = intel_batchbuffer_alloc(intel);
intel->last_swap_fence = NULL;
......@@ -457,11 +542,10 @@ intelInitContext(struct intel_context *intel,
intel->prim.primitive = ~0;
#if DO_DEBUG
INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
if (!intel->intelScreen->ttm && (INTEL_DEBUG & DEBUG_BUFMGR))
dri_bufmgr_fake_set_debug(intel->intelScreen->bufmgr, GL_TRUE);
if (!intel->ttm && (INTEL_DEBUG & DEBUG_BUFMGR))
dri_bufmgr_fake_set_debug(intel->bufmgr, GL_TRUE);
#endif
if (getenv("INTEL_NO_RAST")) {
......@@ -507,6 +591,7 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
intel->first_swap_fence = NULL;
}
dri_bufmgr_destroy(intel->bufmgr);
if (release_texture_heaps) {
/* This share group is about to go away, free our private
......@@ -551,21 +636,21 @@ intelMakeCurrent(__DRIcontextPrivate * driContextPriv,
if (intel_fb->color_rb[0] && !intel_fb->color_rb[0]->region) {
intel_region_reference(&intel_fb->color_rb[0]->region,
intel->intelScreen->front_region);
intel->front_region);
}
if (intel_fb->color_rb[1] && !intel_fb->color_rb[1]->region) {
intel_region_reference(&intel_fb->color_rb[1]->region,
intel->intelScreen->back_region);
intel->back_region);
}
if (intel_fb->color_rb[2] && !intel_fb->color_rb[2]->region) {
intel_region_reference(&intel_fb->color_rb[2]->region,
intel->intelScreen->third_region);
intel->third_region);
}
if (irbDepth && !irbDepth->region) {
intel_region_reference(&irbDepth->region, intel->intelScreen->depth_region);
intel_region_reference(&irbDepth->region, intel->depth_region);
}
if (irbStencil && !irbStencil->region) {
intel_region_reference(&irbStencil->region, intel->intelScreen->depth_region);
intel_region_reference(&irbStencil->region, intel->depth_region);
}
}
......@@ -618,7 +703,6 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
{
__DRIdrawablePrivate *dPriv = intel->driDrawable;
__DRIscreenPrivate *sPriv = intel->driScreen;
intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private;
drmI830Sarea *sarea = intel->sarea;
drmGetLock(intel->driFd, intel->hHWContext, flags);
......@@ -639,9 +723,9 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
* between contexts of a single fake bufmgr, but this will at least make
* things correct for now.
*/
if (!intel->intelScreen->ttm && sarea->texAge != intel->hHWContext) {
if (!intel->ttm && sarea->texAge != intel->hHWContext) {
sarea->texAge = intel->hHWContext;
dri_bufmgr_fake_contended_lock_take(intel->intelScreen->bufmgr);
dri_bufmgr_fake_contended_lock_take(intel->bufmgr);
if (INTEL_DEBUG & DEBUG_BATCH)
intel_decode_context_reset();
}
......
......@@ -34,6 +34,7 @@
#include "drm.h"
#include "mm.h"
#include "texmem.h"
#include "dri_bufmgr.h"
#include "intel_screen.h"
#include "intel_tex_obj.h"
......@@ -142,10 +143,25 @@ struct intel_context
GLuint Fallback;
GLuint NewGLState;
dri_bufmgr *bufmgr;
unsigned int maxBatchSize;
struct intel_region *front_region;
struct intel_region *back_region;
struct intel_region *third_region;
struct intel_region *depth_region;
/**
* This value indicates that the kernel memory manager is being used
* instead of the fake client-side memory manager.
*/
GLboolean ttm;
dri_fence *last_swap_fence;
dri_fence *first_swap_fence;
struct intel_batchbuffer *batch;
unsigned batch_id;
GLuint last_state_batch_id;
struct
......
......@@ -47,15 +47,14 @@
#define FILE_DEBUG_FLAG DEBUG_IOCTL
int
intelEmitIrqLocked(intelScreenPrivate *intelScreen)
intelEmitIrqLocked(struct intel_context *intel)
{
drmI830IrqEmit ie;
int ret, seq;
ie.irq_seq = &seq;
ret = drmCommandWriteRead(intelScreen->driScrnPriv->fd,
DRM_I830_IRQ_EMIT, &ie, sizeof(ie));
ret = drmCommandWriteRead(intel->driFd, DRM_I830_IRQ_EMIT, &ie, sizeof(ie));
if (ret) {
fprintf(stderr, "%s: drmI830IrqEmit: %d\n", __FUNCTION__, ret);
exit(1);
......@@ -67,7 +66,7 @@ intelEmitIrqLocked(intelScreenPrivate *intelScreen)
}
void
intelWaitIrq(intelScreenPrivate *intelScreen, int seq)
intelWaitIrq(struct intel_context *intel, int seq)
{
drm_i915_irq_wait_t iw;
int ret;
......@@ -77,8 +76,7 @@ intelWaitIrq(intelScreenPrivate *intelScreen, int seq)
iw.irq_seq = seq;
do {
ret = drmCommandWrite(intelScreen->driScrnPriv->fd,
DRM_I830_IRQ_WAIT, &iw, sizeof(iw));
ret = drmCommandWrite(intel->driFd, DRM_I830_IRQ_WAIT, &iw, sizeof(iw));
} while (ret == -EAGAIN || ret == -EINTR);
if (ret) {
......@@ -170,7 +168,7 @@ intel_exec_ioctl(struct intel_context *intel,
}
fo = intel_ttm_fence_create_from_arg(intel->intelScreen->bufmgr, "fence buffers",
fo = intel_ttm_fence_create_from_arg(intel->bufmgr, "fence buffers",
&execbuf.fence_arg);
if (!fo) {
fprintf(stderr, "failed to fence handle: %08x\n", execbuf.fence_arg.handle);
......
......@@ -30,8 +30,8 @@
#include "intel_context.h"
void intelWaitIrq(intelScreenPrivate *intelScreen, int seq);
int intelEmitIrqLocked(intelScreenPrivate *intelScreen);
void intelWaitIrq(struct intel_context *intel, int seq);
int intelEmitIrqLocked(struct intel_context *intel);
void intel_batch_ioctl(struct intel_context *intel,
GLuint start_offset,
......
......@@ -54,9 +54,8 @@ copypix_src_region(struct intel_context *intel, GLenum type)
case GL_DEPTH:
/* Don't think this is really possible execpt at 16bpp, when we have no stencil.
*/
if (intel->intelScreen->depth_region &&
intel->intelScreen->depth_region->cpp == 2)
return intel->intelScreen->depth_region;
if (intel->depth_region && intel->depth_region->cpp == 2)
return intel->depth_region;
case GL_STENCIL:
/* Don't think this is really possible.
*/
......@@ -64,7 +63,7 @@ copypix_src_region(struct intel_context *intel, GLenum type)
case GL_DEPTH_STENCIL_EXT:
/* Does it matter whether it is stencil/depth or depth/stencil?
*/
return intel->intelScreen->depth_region;
return intel->depth_region;
default:
break;
}
......@@ -164,7 +163,7 @@ do_texture_copypixels(GLcontext * ctx,
/* Set the 3d engine to draw into the destination region:
*/
intel->vtbl.meta_draw_region(intel, dst, intel->intelScreen->depth_region);
intel->vtbl.meta_draw_region(intel, dst, intel->depth_region);
intel->vtbl.meta_import_pixel_state(intel);
......
......@@ -112,7 +112,7 @@ do_texture_drawpixels(GLcontext * ctx,
/* Set the 3d engine to draw into the destination region:
*/
intel->vtbl.meta_draw_region(intel, dst, intel->intelScreen->depth_region);
intel->vtbl.meta_draw_region(intel, dst, intel->depth_region);
intel->vtbl.meta_import_pixel_state(intel);
......
......@@ -472,7 +472,7 @@ void brw_draw_init( struct brw_context *brw )
/* Set the internal VBOs to no-backing-store. We only use them as a
* temporary within a brw_try_draw_prims while the lock is held.
*/
if (!brw->intel.intelScreen->ttm) {
if (!brw->intel.ttm) {
struct intel_buffer_object *intel_bo =
intel_buffer_object(brw->vb.upload.vbo[i]);
......
......@@ -88,7 +88,7 @@ static void brw_init_pool( struct brw_context *brw,
pool->size = size;
pool->brw = brw;
pool->buffer = dri_bo_alloc(brw->intel.intelScreen->bufmgr,
pool->buffer = dri_bo_alloc(brw->intel.bufmgr,
(pool_id == BRW_GS_POOL) ? "GS pool" : "SS pool",
size, 4096, DRM_BO_FLAG_MEM_TT);
......@@ -97,7 +97,7 @@ static void brw_init_pool( struct brw_context *brw,
* the contents at approximately the same cost as the memcpy, and only
* if the contents are lost.
*/
if (!brw->intel.intelScreen->ttm) {
if (!brw->intel.ttm) {
dri_bo_fake_disable_backing_store(pool->buffer, brw_invalidate_pool_cb,
pool);
}
......
......@@ -81,7 +81,7 @@ static void upload_wm_unit(struct brw_context *brw )
brw->wm.scratch_buffer = NULL;
}
if (!brw->wm.scratch_buffer) {
brw->wm.scratch_buffer = dri_bo_alloc(intel->intelScreen->bufmgr,
brw->wm.scratch_buffer = dri_bo_alloc(intel->bufmgr,
"wm scratch",
brw->wm.scratch_buffer_size,
4096, DRM_BO_FLAG_MEM_TT);
......
......@@ -39,7 +39,7 @@ static void
intel_bufferobj_alloc_buffer(struct intel_context *intel,
struct intel_buffer_object *intel_obj)
{
intel_obj->buffer = dri_bo_alloc(intel->intelScreen->bufmgr, "bufferobj",
intel_obj->buffer = dri_bo_alloc(intel->bufmgr, "bufferobj",
intel_obj->Base.Size, 64,
DRM_BO_FLAG_MEM_TT);
}
......
......@@ -59,8 +59,9 @@
#include "intel_regions.h"
#include "intel_buffer_objects.h"
#include "intel_decode.h"
#include "intel_bufmgr_ttm.h"
#include "dri_bufmgr.h"
#include "i915_drm.h"
#include "utils.h"
#include "vblank.h"
......@@ -315,6 +316,82 @@ intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
intel->stats_wm--;
}
/** Driver-specific fence emit implementation for the fake memory manager. */
static unsigned int
intel_fence_emit(void *private)
{
struct intel_context *intel = (struct intel_context *)private;
unsigned int fence;
/* XXX: Need to emit a flush, if we haven't already (at least with the
* current batchbuffer implementation, we have).
*/
fence = intelEmitIrqLocked(intel);
return fence;
}
/** Driver-specific fence wait implementation for the fake memory manager. */
static int
intel_fence_wait(void *private, unsigned int cookie)
{
struct intel_context *intel = (struct intel_context *)private;
intelWaitIrq(intel, cookie);
return 0;
}
static GLboolean
intel_init_bufmgr(struct intel_context *intel)
{
intelScreenPrivate *intelScreen = intel->intelScreen;
GLboolean ttm_disable = getenv("INTEL_NO_TTM") != NULL;
/* If we've got a new enough DDX that's initializing TTM and giving us
* object handles for the shared buffers, use that.
*/
intel->ttm = GL_FALSE;
if (!ttm_disable &&
intel->intelScreen->driScrnPriv->ddx_version.minor >= 9 &&
intel->intelScreen->drmMinor >= 11 &&
intel->intelScreen->front.bo_handle != -1)
{
intel->bufmgr = intel_bufmgr_ttm_init(intel->driFd,
DRM_FENCE_TYPE_EXE,
DRM_FENCE_TYPE_EXE |
DRM_I915_FENCE_TYPE_RW,
BATCH_SZ);
if (intel->bufmgr != NULL)
intel->ttm = GL_TRUE;
}
/* Otherwise, use the classic buffer manager. */
if (intel->bufmgr == NULL) {
if (ttm_disable) {
fprintf(stderr, "TTM buffer manager disabled. Using classic.\n");
} else {
fprintf(stderr, "Failed to initialize TTM buffer manager. "
"Falling back to classic.\n");
}
if (intelScreen->tex.size == 0) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return GL_FALSE;
}
intel->bufmgr = dri_bufmgr_fake_init(intelScreen->tex.offset,
intelScreen->tex.map,
intelScreen->tex.size,
intel_fence_emit,
intel_fence_wait,
intel);
}
return GL_TRUE;
}
void intelInitDriverFunctions( struct dd_function_table *functions )
{
......@@ -340,24 +417,6 @@ void intelInitDriverFunctions( struct dd_function_table *functions )
intelInitBufferFuncs( functions );
}
static void
intel_update_screen_regions(struct intel_context *intel)
{
intel->bufmgr = intel->intelScreen->bufmgr;
intel_region_release(intel, &intel->front_region);
intel_region_reference(&intel->front_region,
intel->intelScreen->front_region);
intel_region_release(intel, &intel->back_region);
intel_region_reference(&intel->back_region,
intel->intelScreen->back_region);
intel_region_release(intel, &intel->depth_region);
intel_region_reference(&intel->depth_region,
intel->intelScreen->depth_region);
}
GLboolean intelInitContext( struct intel_context *intel,
const __GLcontextModes *mesaVis,
__DRIcontextPrivate *driContextPriv,
......@@ -384,6 +443,16 @@ GLboolean intelInitContext( struct intel_context *intel,
intel->driScreen = sPriv;
intel->sarea = saPriv;
/* Dri stuff */
intel->hHWContext = driContextPriv->hHWContext;
intel->driFd = sPriv->fd;
intel->driHwLock = (drmLock *) &sPriv->pSAREA->lock;
intel->maxBatchSize = BATCH_SZ;
if (!intel_init_bufmgr(intel))
return GL_FALSE;
driParseConfigFiles (&intel->optionCache, &intelScreen->optionCache,
intel->driScreen->myNum, "i965");
......@@ -431,11 +500,6 @@ GLboolean intelInitContext( struct intel_context *intel,
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
/* Dri stuff */
intel->hHWContext = driContextPriv->hHWContext;
intel->driFd = sPriv->fd;
intel->driHwLock = (drmLock *) &sPriv->pSAREA->lock;
intel->hw_stencil = mesaVis->stencilBits && mesaVis->depthBits == 24;
intel->hw_stipple = 1;
......@@ -470,10 +534,10 @@ GLboolean intelInitContext( struct intel_context *intel,
INTEL_DEBUG = driParseDebugString( getenv( "INTEL_DEBUG" ),
debug_control );
if (!intel->intelScreen->ttm && (INTEL_DEBUG & DEBUG_BUFMGR))
dri_bufmgr_fake_set_debug(intel->intelScreen->bufmgr, GL_TRUE);
if (!intel->ttm && (INTEL_DEBUG & DEBUG_BUFMGR))
dri_bufmgr_fake_set_debug(intel->bufmgr, GL_TRUE);
intel_update_screen_regions(intel);
intel_recreate_static_regions(intel);
intel_bufferobj_init( intel );
intel->batch = intel_batchbuffer_alloc( intel );
......@@ -493,12 +557,16 @@ GLboolean intelInitContext( struct intel_context *intel,
/* DRI_TEXMGR_DO_TEXTURE_2D | */
/* DRI_TEXMGR_DO_TEXTURE_RECT ); */
/* Force all software fallbacks */
if (getenv("INTEL_NO_RAST")) {
fprintf(stderr, "disabling 3D rasterization\n");
intel->no_rast = 1;
}
/* Disable all hardware rendering (skip emitting batches and fences/waits
* to the kernel)
*/
intel->no_hw = getenv("INTEL_NO_HW") != NULL;
return GL_TRUE;
}
......@@ -643,9 +711,9 @@ static void intelContendedLock( struct intel_context *intel, GLuint flags )
* between contexts of a single fake bufmgr, but this will at least make
* things correct for now.
*/
if (!intel->intelScreen->ttm && sarea->texAge != intel->hHWContext) {
if (!intel->ttm && sarea->texAge != intel->hHWContext) {
sarea->texAge = intel->hHWContext;
dri_bufmgr_fake_contended_lock_take(intel->intelScreen->bufmgr);
dri_bufmgr_fake_contended_lock_take(intel->bufmgr);
if (INTEL_DEBUG & DEBUG_BATCH)
intel_decode_context_reset();
if (INTEL_DEBUG & DEBUG_BUFMGR) {
......
......@@ -157,13 +157,28 @@ struct intel_context
GLint refcount;
GLuint Fallback;
GLuint NewGLState;
dri_bufmgr *bufmgr;
unsigned int maxBatchSize;
struct intel_region *front_region;
struct intel_region *back_region;
struct intel_region *third_region;
struct intel_region *depth_region;
/**
* This value indicates that the kernel memory manager is being used
* instead of the fake client-side memory manager.
*/
GLboolean ttm;
dri_fence *first_swap_fence;
dri_fence *last_swap_fence;
GLuint stats_wm;
struct intel_batchbuffer *batch;
unsigned batch_id;
GLubyte clear_chan[4];
GLuint ClearColor;
......@@ -205,12 +220,6 @@ struct intel_context
drmLock *driHwLock;
int driFd;
/* Cached values from the screen private. */
dri_bufmgr *bufmgr;
struct intel_region *front_region;
struct intel_region *back_region;
struct intel_region *depth_region;
__DRIdrawablePrivate *driDrawable;
__DRIdrawablePrivate *driReadDrawable;
__DRIscreenPrivate *driScreen;
......@@ -219,6 +228,8 @@ struct intel_context
GLuint lastStamp;
GLboolean no_hw;
/**
* Configuration cache
*/
......
......@@ -52,15 +52,15 @@ static void intelWaitIdleLocked( struct intel_context *intel )
if (INTEL_DEBUG & DEBUG_SYNC)
fprintf(stderr, "waiting for idle\n");
fence = intelEmitIrqLocked(intel->intelScreen);
intelWaitIrq(intel->intelScreen, fence);
fence = intelEmitIrqLocked(intel);
intelWaitIrq(intel, fence);
}
int intelEmitIrqLocked( intelScreenPrivate *intelScreen )
int intelEmitIrqLocked( struct intel_context *intel )
{
int seq = 1;
if (!intelScreen->no_hw) {
if (!intel->no_hw) {
drmI830IrqEmit ie;
int ret;
/*
......@@ -69,7 +69,7 @@ int intelEmitIrqLocked( intelScreenPrivate *intelScreen )
*/
ie.irq_seq = &seq;
ret = drmCommandWriteRead( intelScreen->driScrnPriv->fd,
ret = drmCommandWriteRead( intel->driFd,
DRM_I830_IRQ_EMIT,
&ie, sizeof(ie) );
if ( ret ) {
......@@ -84,14 +84,12 @@ int intelEmitIrqLocked( intelScreenPrivate *intelScreen )
return seq;
}
void intelWaitIrq( intelScreenPrivate *intelScreen, int seq )
void intelWaitIrq( struct intel_context *intel, int seq )
{
if (!intelScreen->no_hw) {
if (!intel->no_hw) {
drmI830IrqWait iw;
int ret, lastdispatch;
volatile drmI830Sarea *sarea = (volatile drmI830Sarea *)
(((GLubyte *)intelScreen->driScrnPriv->pSAREA) +
intelScreen->sarea_priv_offset);
volatile drmI830Sarea *sarea = intel->sarea;
if (0)
fprintf(stderr, "%s %d\n", __FUNCTION__, seq );
......@@ -100,7 +98,7 @@ void intelWaitIrq( intelScreenPrivate *intelScreen, int seq )
do {
lastdispatch = sarea->last_dispatch;
ret = drmCommandWrite( intelScreen->driScrnPriv->fd,
ret = drmCommandWrite( intel->driFd,
DRM_I830_IRQ_WAIT, &iw, sizeof(iw) );
/* This seems quite often to return before it should!?!
......@@ -151,7 +149,7 @@ void intel_batch_ioctl( struct intel_context *intel,
batch.start,
batch.start + batch.used * 4);
if (!intel->intelScreen->no_hw) {
if (!intel->no_hw) {
if (drmCommandWrite (intel->driFd, DRM_I830_BATCHBUFFER, &batch,
sizeof(batch))) {
fprintf(stderr, "DRM_I830_BATCHBUFFER: %d\n", -errno);
......@@ -190,7 +188,7 @@ intel_exec_ioctl(struct intel_context *intel,
execbuf.ops_list = (unsigned)start; // TODO
execbuf.fence_arg.flags = DRM_FENCE_FLAG_SHAREABLE | DRM_I915_FENCE_FLAG_FLUSHED;
if (intel->intelScreen->no_hw)
if (intel->no_hw)
return;
if (drmCommandWriteRead(intel->driFd, DRM_I915_EXECBUFFER, &execbuf,
......@@ -201,7 +199,7 @@ intel_exec_ioctl(struct intel_context *intel,
}
fo = intel_ttm_fence_create_from_arg(intel->intelScreen->bufmgr, "fence buffers",
fo = intel_ttm_fence_create_from_arg(intel->bufmgr, "fence buffers",
&execbuf.fence_arg);
if (!fo) {
fprintf(stderr, "failed to fence handle: %08x\n", execbuf.fence_arg.handle);
......
......@@ -30,8 +30,8 @@
#include "intel_context.h"
void intelWaitIrq( intelScreenPrivate *intelScreen, int seq );
int intelEmitIrqLocked( intelScreenPrivate *intelScreen );
void intelWaitIrq( struct intel_context *intel, int seq );
int intelEmitIrqLocked( struct intel_context *intel );
void intel_batch_ioctl( struct intel_context *intel,