Commit 3f2a0649 authored by Marek Olšák's avatar Marek Olšák

radeonsi: adjust ESGS ring buffer size computation on VI

Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
parent 80814819
......@@ -2115,7 +2115,10 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
unsigned num_se = sctx->screen->b.info.max_se;
unsigned wave_size = 64;
unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
/* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
* On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
*/
unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
......
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