Skip to content
  • Matt Turner's avatar
    intel/compiler: Add Gen11+ native float type · 2cff3242
    Matt Turner authored
    
    
    This new type exposes the additional precision offered by the
    accumulator register and will be used in the next patch to implement the
    functionality of the PLN instruction using a pair of MAD instructions.
    
    One weird thing to note: align1 ternary instructions may only have an
    accumulator in the dst or src1 normally, but when src0's type is :NF
    the accumulator is read.
    
    Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
    2cff3242