Commit b5d8781e authored by Matt Turner's avatar Matt Turner

intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

If multiple instructions are emitted, special handling of things like
conditional mod and NoDDClr/NoDDChk need to be performed.
Reviewed-by: Kenneth Graunke (semi-AFK still)'s avatarKenneth Graunke <kenneth@whitecape.org>
parent b1afdf9f
...@@ -409,7 +409,7 @@ private: ...@@ -409,7 +409,7 @@ private:
void generate_urb_write(fs_inst *inst, struct brw_reg payload); void generate_urb_write(fs_inst *inst, struct brw_reg payload);
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload); void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
void generate_barrier(fs_inst *inst, struct brw_reg src); void generate_barrier(fs_inst *inst, struct brw_reg src);
void generate_linterp(fs_inst *inst, struct brw_reg dst, bool generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src); struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src, void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
struct brw_reg surface_index, struct brw_reg surface_index,
......
...@@ -646,9 +646,9 @@ fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src) ...@@ -646,9 +646,9 @@ fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
brw_WAIT(p); brw_WAIT(p);
} }
void bool
fs_generator::generate_linterp(fs_inst *inst, fs_generator::generate_linterp(fs_inst *inst,
struct brw_reg dst, struct brw_reg *src) struct brw_reg dst, struct brw_reg *src)
{ {
/* PLN reads: /* PLN reads:
* / in SIMD16 \ * / in SIMD16 \
...@@ -678,6 +678,8 @@ fs_generator::generate_linterp(fs_inst *inst, ...@@ -678,6 +678,8 @@ fs_generator::generate_linterp(fs_inst *inst,
if (devinfo->has_pln && if (devinfo->has_pln &&
(devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) { (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
brw_PLN(p, dst, interp, delta_x); brw_PLN(p, dst, interp, delta_x);
return false;
} else { } else {
i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x); i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y); i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
...@@ -689,6 +691,8 @@ fs_generator::generate_linterp(fs_inst *inst, ...@@ -689,6 +691,8 @@ fs_generator::generate_linterp(fs_inst *inst,
* the first instruction. * the first instruction.
*/ */
brw_inst_set_saturate(p->devinfo, i[0], false); brw_inst_set_saturate(p->devinfo, i[0], false);
return true;
} }
} }
...@@ -1963,7 +1967,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) ...@@ -1963,7 +1967,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
brw_MOV(p, dst, src[0]); brw_MOV(p, dst, src[0]);
break; break;
case FS_OPCODE_LINTERP: case FS_OPCODE_LINTERP:
generate_linterp(inst, dst, src); multiple_instructions_emitted = generate_linterp(inst, dst, src);
break; break;
case FS_OPCODE_PIXEL_X: case FS_OPCODE_PIXEL_X:
assert(src[0].type == BRW_REGISTER_TYPE_UW); assert(src[0].type == BRW_REGISTER_TYPE_UW);
......
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