Commit 60d8fe92 authored by Kenneth Graunke's avatar Kenneth Graunke

i965: Delete completely bogus comment

This hasn't been true in 6+ years, if it was even true then.  Before
we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used
to have two compiler backends for WM programs, based on Mesa IR.  One
handled flow control and was SIMD8-only, while the other was SIMD16
only and didn't handle flow control.  Or something like that.

Even then, this certainly didn't handle vertex shaders, so "all ...
code generation" is a bit strong.
parent 436ed65d
......@@ -126,11 +126,6 @@ brw_wm_debug_recompile(struct brw_context *brw, struct gl_program *prog,
}
}
/**
* All Mesa program -> GPU code generation goes through this function.
* Depending on the instructions used (i.e. flow control instructions)
* we'll use one of two code generators.
*/
static bool
brw_codegen_wm_prog(struct brw_context *brw,
struct brw_program *fp,
......
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