... | ... | @@ -23,10 +23,13 @@ Tessellation Control Shaders |
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### Inputs
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Presumably the specific regid's are configurable via some register, but I've been unable to get the RA to assign it to anything else, so no idea which bitfield to look in.
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* `r0.x` -- This value contains a bitfield:
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* Bits 0:4 : primitive offset in buffer
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* Bits 10:14 : `gl_InvocationID`
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* `r0.y` -- `gl_PrimitiveID`
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* `r0.z` -- primitive number in patch "buffer". Used to compute the offset in the tessfactor patch outputs, as well as regular patch outputs.
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See [[A4xx Geometry Shaders]] for how inputs are read in with `ldlw`. The same logic follows here. The input primitive size is based on `gl_PatchVerticesIn`, which comes in via a driver-supplied const.
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### Outputs
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There are no regid-based outputs from a hull shader. It writes all of its data into gmem. In order to interact with the other hull shaders, it first stages all of its outputs (including per-vertex) outputs into "private" memory, accessible via `stp` and `ldp`, and then invocation 0 writes all of them out into global memory. The layout of the tess factors is fixed since the hardware has to read it in, but the regular patch outputs and per-vertex outputs are free-form and up to the driver -- just have to match to what the domain shader expects to read in.
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